arm: Make memory ops work on 64bit/128-bit quantities
Multiple instructions assume only 32-bit load operations are available, this patch increases load sizes to 64-bit or 128-bit for many load pair and load multiple instructions.
This commit is contained in:
parent
f6f63ec0aa
commit
8f95144e16
6 changed files with 360 additions and 213 deletions
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@ -61,14 +61,29 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
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{
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uint32_t regs = reglist;
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uint32_t ones = number_of_ones(reglist);
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// Remember that writeback adds a uop or two and the temp register adds one
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numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1;
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uint32_t mem_ops = ones;
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// It's technically legal to do a lot of nothing
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if (!ones)
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// Copy the base address register if we overwrite it, or if this instruction
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// is basically a no-op (we have to do something)
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bool copy_base = (bits(reglist, rn) && load) || !ones;
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bool force_user = user & !bits(reglist, 15);
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bool exception_ret = user & bits(reglist, 15);
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bool pc_temp = load && writeback && bits(reglist, 15);
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if (!ones) {
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numMicroops = 1;
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} else if (load) {
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numMicroops = ((ones + 1) / 2)
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+ ((ones % 2 == 0 && exception_ret) ? 1 : 0)
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+ (copy_base ? 1 : 0)
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+ (writeback? 1 : 0)
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+ (pc_temp ? 1 : 0);
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} else {
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numMicroops = ones + (writeback ? 1 : 0);
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}
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microOps = new StaticInstPtr[numMicroops];
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uint32_t addr = 0;
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if (!up)
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@ -81,94 +96,129 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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*uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
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if (copy_base)
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*uop++ = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
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unsigned reg = 0;
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unsigned regIdx = 0;
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bool force_user = user & !bits(reglist, 15);
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bool exception_ret = user & bits(reglist, 15);
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while (mem_ops != 0) {
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// Do load operations in pairs if possible
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if (load && mem_ops >= 2 &&
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!(mem_ops == 2 && bits(regs,INTREG_PC) && exception_ret)) {
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// 64-bit memory operation
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// Find 2 set register bits (clear them after finding)
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unsigned reg_idx1;
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unsigned reg_idx2;
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for (int i = 0; i < ones; i++) {
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// Find the next register.
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while (!bits(regs, reg))
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reg++;
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// Find the first register
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while (!bits(regs, reg)) reg++;
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replaceBits(regs, reg, 0);
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reg_idx1 = force_user ? intRegInMode(MODE_USER, reg) : reg;
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regIdx = reg;
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if (force_user) {
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regIdx = intRegInMode(MODE_USER, regIdx);
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// Find the second register
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while (!bits(regs, reg)) reg++;
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replaceBits(regs, reg, 0);
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reg_idx2 = force_user ? intRegInMode(MODE_USER, reg) : reg;
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// Load into temp reg if necessary
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if (reg_idx2 == INTREG_PC && pc_temp)
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reg_idx2 = INTREG_UREG1;
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// Actually load both registers from memory
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*uop = new MicroLdr2Uop(machInst, reg_idx1, reg_idx2,
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copy_base ? INTREG_UREG0 : rn, up, addr);
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if (!writeback && reg_idx2 == INTREG_PC) {
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// No writeback if idx==pc, set appropriate flags
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(*uop)->setFlag(StaticInst::IsControl);
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(*uop)->setFlag(StaticInst::IsIndirectControl);
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if (!(condCode == COND_AL || condCode == COND_UC))
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(*uop)->setFlag(StaticInst::IsCondControl);
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else
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(*uop)->setFlag(StaticInst::IsUncondControl);
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}
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if (up) addr += 8;
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else addr -= 8;
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mem_ops -= 2;
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} else {
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// 32-bit memory operation
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// Find register for operation
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unsigned reg_idx;
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while(!bits(regs, reg)) reg++;
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replaceBits(regs, reg, 0);
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reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg;
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if (load) {
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if (writeback && i == ones - 1) {
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// If it's a writeback and this is the last register
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// do the load into a temporary register which we'll move
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// into the final one later
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*++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0,
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up, addr);
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if (writeback && reg_idx == INTREG_PC) {
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// If this instruction changes the PC and performs a
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// writeback, ensure the pc load/branch is the last uop.
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// Load into a temp reg here.
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*uop = new MicroLdrUop(machInst, INTREG_UREG1,
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copy_base ? INTREG_UREG0 : rn, up, addr);
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} else if (reg_idx == INTREG_PC && exception_ret) {
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// Special handling for exception return
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*uop = new MicroLdrRetUop(machInst, reg_idx,
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copy_base ? INTREG_UREG0 : rn, up, addr);
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} else {
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// Otherwise just do it normally
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if (reg == INTREG_PC && exception_ret) {
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// This must be the exception return form of ldm.
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*++uop = new MicroLdrRetUop(machInst, regIdx,
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INTREG_UREG0, up, addr);
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if (!(condCode == COND_AL || condCode == COND_UC))
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(*uop)->setFlag(StaticInst::IsCondControl);
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else
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(*uop)->setFlag(StaticInst::IsUncondControl);
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} else {
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*++uop = new MicroLdrUop(machInst, regIdx,
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INTREG_UREG0, up, addr);
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if (reg == INTREG_PC) {
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(*uop)->setFlag(StaticInst::IsControl);
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if (!(condCode == COND_AL || condCode == COND_UC))
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(*uop)->setFlag(StaticInst::IsCondControl);
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else
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(*uop)->setFlag(StaticInst::IsUncondControl);
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(*uop)->setFlag(StaticInst::IsIndirectControl);
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}
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}
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}
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} else {
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*++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
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// standard single load uop
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*uop = new MicroLdrUop(machInst, reg_idx,
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copy_base ? INTREG_UREG0 : rn, up, addr);
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}
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if (up)
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addr += 4;
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// Loading pc as last operation? Set appropriate flags.
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if (!writeback && reg_idx == INTREG_PC) {
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(*uop)->setFlag(StaticInst::IsControl);
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(*uop)->setFlag(StaticInst::IsIndirectControl);
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if (!(condCode == COND_AL || condCode == COND_UC))
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(*uop)->setFlag(StaticInst::IsCondControl);
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else
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addr -= 4;
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(*uop)->setFlag(StaticInst::IsUncondControl);
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}
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} else {
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*uop = new MicroStrUop(machInst, reg_idx, rn, up, addr);
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}
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if (up) addr += 4;
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else addr -= 4;
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--mem_ops;
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}
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// Load/store micro-op generated, go to next uop
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++uop;
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}
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if (writeback && ones) {
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// put the register update after we're done all loading
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// Perform writeback uop operation
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if (up)
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*++uop = new MicroAddiUop(machInst, rn, rn, ones * 4);
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*uop++ = new MicroAddiUop(machInst, rn, rn, ones * 4);
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else
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*++uop = new MicroSubiUop(machInst, rn, rn, ones * 4);
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*uop++ = new MicroSubiUop(machInst, rn, rn, ones * 4);
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// Write PC after address writeback?
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if (pc_temp) {
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if (exception_ret) {
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*uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
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} else {
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*uop = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG1);
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}
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(*uop)->setFlag(StaticInst::IsControl);
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(*uop)->setFlag(StaticInst::IsIndirectControl);
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// If this was a load move the last temporary value into place
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// this way we can't take an exception after we update the base
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// register.
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if (load && reg == INTREG_PC && exception_ret) {
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*++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
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if (!(condCode == COND_AL || condCode == COND_UC))
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(*uop)->setFlag(StaticInst::IsCondControl);
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else
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(*uop)->setFlag(StaticInst::IsUncondControl);
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} else if (load) {
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*++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1);
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if (reg == INTREG_PC) {
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(*uop)->setFlag(StaticInst::IsControl);
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(*uop)->setFlag(StaticInst::IsCondControl);
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(*uop)->setFlag(StaticInst::IsIndirectControl);
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// This is created as a RAS POP
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if (rn == INTREG_SP)
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(*uop)->setFlag(StaticInst::IsReturn);
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}
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++uop;
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}
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}
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--uop;
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(*uop)->setLastMicroop();
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/* Take the control flags from the last microop for the macroop */
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@ -176,16 +226,15 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
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setFlag(StaticInst::IsControl);
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if ((*uop)->isCondCtrl())
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setFlag(StaticInst::IsCondControl);
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if ((*uop)->isUncondCtrl())
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setFlag(StaticInst::IsUncondControl);
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if ((*uop)->isIndirectCtrl())
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setFlag(StaticInst::IsIndirectControl);
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if ((*uop)->isReturn())
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setFlag(StaticInst::IsReturn);
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
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assert(uopPtr);
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uopPtr->setDelayedCommit();
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for (StaticInstPtr *uop = microOps; !(*uop)->isLastMicroop(); uop++) {
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(*uop)->setDelayedCommit();
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}
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}
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@ -196,95 +245,96 @@ PairMemOp::PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) :
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PredMacroOp(mnem, machInst, __opClass)
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{
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bool post = (mode == AddrMd_PostIndex);
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bool writeback = (mode != AddrMd_Offset);
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numMicroops = 1 + (size / 4) + (writeback ? 1 : 0);
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if (load) {
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// Use integer rounding to round up loads of size 4
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numMicroops = (post ? 0 : 1) + ((size + 4) / 8) + (writeback ? 1 : 0);
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} else {
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numMicroops = (post ? 0 : 1) + (size / 4) + (writeback ? 1 : 0);
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}
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microOps = new StaticInstPtr[numMicroops];
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StaticInstPtr *uop = microOps;
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bool post = (mode == AddrMd_PostIndex);
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rn = makeSP(rn);
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*uop = new MicroAddXiSpAlignUop(machInst, INTREG_UREG0, rn, post ? 0 : imm);
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if (!post) {
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*uop++ = new MicroAddXiSpAlignUop(machInst, INTREG_UREG0, rn,
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post ? 0 : imm);
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}
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if (fp) {
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if (size == 16) {
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if (load) {
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*++uop = new MicroLdrQBFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroLdrQTFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroLdrQBFpXImmUop(machInst, rt2,
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INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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*++uop = new MicroLdrQTFpXImmUop(machInst, rt2,
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INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdFp16Uop(machInst, rt,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdFp16Uop(machInst, rt2,
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post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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} else {
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*++uop = new MicroStrQBFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroStrQTFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroStrQBFpXImmUop(machInst, rt2,
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INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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*++uop = new MicroStrQTFpXImmUop(machInst, rt2,
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INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrQBFpXImmUop(machInst, rt,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrQTFpXImmUop(machInst, rt,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrQBFpXImmUop(machInst, rt2,
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post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrQTFpXImmUop(machInst, rt2,
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post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
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}
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} else if (size == 8) {
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if (load) {
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*++uop = new MicroLdrFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroLdrFpXImmUop(machInst, rt2,
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INTREG_UREG0, 8, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdPairFp8Uop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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} else {
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*++uop = new MicroStrFpXImmUop(machInst, rt,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*++uop = new MicroStrFpXImmUop(machInst, rt2,
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INTREG_UREG0, 8, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrFpXImmUop(machInst, rt,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrFpXImmUop(machInst, rt2,
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post ? rn : INTREG_UREG0, 8, noAlloc, exclusive, acrel);
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}
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} else if (size == 4) {
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if (load) {
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*++uop = new MicroLdrDFpXImmUop(machInst, rt, rt2,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdrDFpXImmUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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} else {
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*++uop = new MicroStrDFpXImmUop(machInst, rt, rt2,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrDFpXImmUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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}
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}
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} else {
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if (size == 8) {
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if (load) {
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*++uop = new MicroLdrXImmUop(machInst, rt, INTREG_UREG0,
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0, noAlloc, exclusive, acrel);
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*++uop = new MicroLdrXImmUop(machInst, rt2, INTREG_UREG0,
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size, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdPairUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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} else {
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*++uop = new MicroStrXImmUop(machInst, rt, INTREG_UREG0,
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*uop++ = new MicroStrXImmUop(machInst, rt, post ? rn : INTREG_UREG0,
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0, noAlloc, exclusive, acrel);
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*++uop = new MicroStrXImmUop(machInst, rt2, INTREG_UREG0,
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*uop++ = new MicroStrXImmUop(machInst, rt2, post ? rn : INTREG_UREG0,
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size, noAlloc, exclusive, acrel);
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}
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} else if (size == 4) {
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if (load) {
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if (signExt) {
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*++uop = new MicroLdrDSXImmUop(machInst, rt, rt2,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdrDSXImmUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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} else {
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*++uop = new MicroLdrDUXImmUop(machInst, rt, rt2,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroLdrDUXImmUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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}
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} else {
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*++uop = new MicroStrDXImmUop(machInst, rt, rt2,
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INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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*uop++ = new MicroStrDXImmUop(machInst, rt, rt2,
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post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
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}
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}
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}
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if (writeback) {
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*++uop = new MicroAddXiUop(machInst, rn, INTREG_UREG0,
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*uop++ = new MicroAddXiUop(machInst, rn, post ? rn : INTREG_UREG0,
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post ? imm : 0);
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}
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(*uop)->setLastMicroop();
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assert(uop == µOps[numMicroops]);
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(*--uop)->setLastMicroop();
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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@ -297,18 +347,19 @@ BigFpMemImmOp::BigFpMemImmOp(const char *mnem, ExtMachInst machInst,
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IntRegIndex base, int64_t imm) :
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PredMacroOp(mnem, machInst, __opClass)
|
||||
{
|
||||
numMicroops = 2;
|
||||
numMicroops = load ? 1 : 2;
|
||||
microOps = new StaticInstPtr[numMicroops];
|
||||
|
||||
StaticInstPtr *uop = microOps;
|
||||
|
||||
if (load) {
|
||||
microOps[0] = new MicroLdrQBFpXImmUop(machInst, dest, base, imm);
|
||||
microOps[1] = new MicroLdrQTFpXImmUop(machInst, dest, base, imm);
|
||||
*uop = new MicroLdFp16Uop(machInst, dest, base, imm);
|
||||
} else {
|
||||
microOps[0] = new MicroStrQBFpXImmUop(machInst, dest, base, imm);
|
||||
microOps[1] = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
|
||||
*uop = new MicroStrQBFpXImmUop(machInst, dest, base, imm);
|
||||
(*uop)->setDelayedCommit();
|
||||
*++uop = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
|
||||
}
|
||||
microOps[0]->setDelayedCommit();
|
||||
microOps[1]->setLastMicroop();
|
||||
(*uop)->setLastMicroop();
|
||||
}
|
||||
|
||||
BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst,
|
||||
|
@ -316,21 +367,24 @@ BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst,
|
|||
IntRegIndex base, int64_t imm) :
|
||||
PredMacroOp(mnem, machInst, __opClass)
|
||||
{
|
||||
numMicroops = 3;
|
||||
numMicroops = load ? 2 : 3;
|
||||
microOps = new StaticInstPtr[numMicroops];
|
||||
|
||||
if (load) {
|
||||
microOps[0] = new MicroLdrQBFpXImmUop(machInst, dest, base, 0);
|
||||
microOps[1] = new MicroLdrQTFpXImmUop(machInst, dest, base, 0);
|
||||
} else {
|
||||
microOps[0] = new MicroStrQBFpXImmUop(machInst, dest, base, 0);
|
||||
microOps[1] = new MicroStrQTFpXImmUop(machInst, dest, base, 0);
|
||||
}
|
||||
microOps[2] = new MicroAddXiUop(machInst, base, base, imm);
|
||||
StaticInstPtr *uop = microOps;
|
||||
|
||||
microOps[0]->setDelayedCommit();
|
||||
microOps[1]->setDelayedCommit();
|
||||
microOps[2]->setLastMicroop();
|
||||
if (load) {
|
||||
*uop++ = new MicroLdFp16Uop(machInst, dest, base, 0);
|
||||
} else {
|
||||
*uop++= new MicroStrQBFpXImmUop(machInst, dest, base, 0);
|
||||
*uop++ = new MicroStrQTFpXImmUop(machInst, dest, base, 0);
|
||||
}
|
||||
*uop = new MicroAddXiUop(machInst, base, base, imm);
|
||||
(*uop)->setLastMicroop();
|
||||
|
||||
for (StaticInstPtr *curUop = microOps;
|
||||
!(*curUop)->isLastMicroop(); curUop++) {
|
||||
(*curUop)->setDelayedCommit();
|
||||
}
|
||||
}
|
||||
|
||||
BigFpMemPreOp::BigFpMemPreOp(const char *mnem, ExtMachInst machInst,
|
||||
|
@ -338,21 +392,24 @@ BigFpMemPreOp::BigFpMemPreOp(const char *mnem, ExtMachInst machInst,
|
|||
IntRegIndex base, int64_t imm) :
|
||||
PredMacroOp(mnem, machInst, __opClass)
|
||||
{
|
||||
numMicroops = 3;
|
||||
numMicroops = load ? 2 : 3;
|
||||
microOps = new StaticInstPtr[numMicroops];
|
||||
|
||||
if (load) {
|
||||
microOps[0] = new MicroLdrQBFpXImmUop(machInst, dest, base, imm);
|
||||
microOps[1] = new MicroLdrQTFpXImmUop(machInst, dest, base, imm);
|
||||
} else {
|
||||
microOps[0] = new MicroStrQBFpXImmUop(machInst, dest, base, imm);
|
||||
microOps[1] = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
|
||||
}
|
||||
microOps[2] = new MicroAddXiUop(machInst, base, base, imm);
|
||||
StaticInstPtr *uop = microOps;
|
||||
|
||||
microOps[0]->setDelayedCommit();
|
||||
microOps[1]->setDelayedCommit();
|
||||
microOps[2]->setLastMicroop();
|
||||
if (load) {
|
||||
*uop++ = new MicroLdFp16Uop(machInst, dest, base, imm);
|
||||
} else {
|
||||
*uop++ = new MicroStrQBFpXImmUop(machInst, dest, base, imm);
|
||||
*uop++ = new MicroStrQTFpXImmUop(machInst, dest, base, imm);
|
||||
}
|
||||
*uop = new MicroAddXiUop(machInst, base, base, imm);
|
||||
(*uop)->setLastMicroop();
|
||||
|
||||
for (StaticInstPtr *curUop = microOps;
|
||||
!(*curUop)->isLastMicroop(); curUop++) {
|
||||
(*curUop)->setDelayedCommit();
|
||||
}
|
||||
}
|
||||
|
||||
BigFpMemRegOp::BigFpMemRegOp(const char *mnem, ExtMachInst machInst,
|
||||
|
@ -361,23 +418,23 @@ BigFpMemRegOp::BigFpMemRegOp(const char *mnem, ExtMachInst machInst,
|
|||
ArmExtendType type, int64_t imm) :
|
||||
PredMacroOp(mnem, machInst, __opClass)
|
||||
{
|
||||
numMicroops = 2;
|
||||
numMicroops = load ? 1 : 2;
|
||||
microOps = new StaticInstPtr[numMicroops];
|
||||
|
||||
StaticInstPtr *uop = microOps;
|
||||
|
||||
if (load) {
|
||||
microOps[0] = new MicroLdrQBFpXRegUop(machInst, dest, base,
|
||||
offset, type, imm);
|
||||
microOps[1] = new MicroLdrQTFpXRegUop(machInst, dest, base,
|
||||
*uop = new MicroLdFp16RegUop(machInst, dest, base,
|
||||
offset, type, imm);
|
||||
} else {
|
||||
microOps[0] = new MicroStrQBFpXRegUop(machInst, dest, base,
|
||||
*uop = new MicroStrQBFpXRegUop(machInst, dest, base,
|
||||
offset, type, imm);
|
||||
microOps[1] = new MicroStrQTFpXRegUop(machInst, dest, base,
|
||||
(*uop)->setDelayedCommit();
|
||||
*++uop = new MicroStrQTFpXRegUop(machInst, dest, base,
|
||||
offset, type, imm);
|
||||
}
|
||||
|
||||
microOps[0]->setDelayedCommit();
|
||||
microOps[1]->setLastMicroop();
|
||||
(*uop)->setLastMicroop();
|
||||
}
|
||||
|
||||
BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst,
|
||||
|
@ -385,14 +442,11 @@ BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst,
|
|||
int64_t imm) :
|
||||
PredMacroOp(mnem, machInst, __opClass)
|
||||
{
|
||||
numMicroops = 2;
|
||||
numMicroops = 1;
|
||||
microOps = new StaticInstPtr[numMicroops];
|
||||
|
||||
microOps[0] = new MicroLdrQBFpXLitUop(machInst, dest, imm);
|
||||
microOps[1] = new MicroLdrQTFpXLitUop(machInst, dest, imm);
|
||||
|
||||
microOps[0]->setDelayedCommit();
|
||||
microOps[1]->setLastMicroop();
|
||||
microOps[0] = new MicroLdFp16LitUop(machInst, dest, imm);
|
||||
microOps[0]->setLastMicroop();
|
||||
}
|
||||
|
||||
VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
|
||||
|
@ -1538,4 +1592,20 @@ MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
|||
return ss.str();
|
||||
}
|
||||
|
||||
std::string
|
||||
MicroMemPairOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
printMnemonic(ss);
|
||||
printReg(ss, dest);
|
||||
ss << ",";
|
||||
printReg(ss, dest2);
|
||||
ss << ", [";
|
||||
printReg(ss, urb);
|
||||
ss << ", ";
|
||||
ccprintf(ss, "#%d", imm);
|
||||
ss << "]";
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013 ARM Limited
|
||||
* Copyright (c) 2010-2014 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
|
@ -395,6 +395,26 @@ class MicroMemOp : public MicroIntImmOp
|
|||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
class MicroMemPairOp : public MicroOp
|
||||
{
|
||||
protected:
|
||||
RegIndex dest, dest2, urb;
|
||||
bool up;
|
||||
int32_t imm;
|
||||
unsigned memAccessFlags;
|
||||
|
||||
MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
|
||||
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
|
||||
bool _up, uint8_t _imm)
|
||||
: MicroOp(mnem, machInst, __opClass),
|
||||
dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
|
||||
memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for microcoded integer memory instructions.
|
||||
*/
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2011-2013 ARM Limited
|
||||
// Copyright (c) 2011-2014 ARM Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// The license below extends only to copyright in the software and shall
|
||||
|
@ -187,34 +187,31 @@ let {{
|
|||
AA64FpDestP2_uw = 0;
|
||||
AA64FpDestP3_uw = 0;
|
||||
'''
|
||||
elif self.size == 8 or (self.size == 16 and not self.top):
|
||||
elif self.size == 8:
|
||||
accCode = '''
|
||||
uint64_t data = cSwap(Mem%s,
|
||||
isBigEndian64(xc->tcBase()));
|
||||
AA64FpDestP0_uw = (uint32_t)data;
|
||||
AA64FpDestP1_uw = (data >> 32);
|
||||
'''
|
||||
# Only zero out the other half if this isn't part of a
|
||||
# pair of 8 byte loads implementing a 16 byte load.
|
||||
if self.size == 8:
|
||||
accCode += '''
|
||||
AA64FpDestP2_uw = 0;
|
||||
AA64FpDestP3_uw = 0;
|
||||
'''
|
||||
elif self.size == 16 and self.top:
|
||||
elif self.size == 16:
|
||||
accCode = '''
|
||||
uint64_t data = cSwap(Mem%s,
|
||||
Twin64_t data = cSwap(Mem%s,
|
||||
isBigEndian64(xc->tcBase()));
|
||||
AA64FpDestP2_uw = (uint32_t)data;
|
||||
AA64FpDestP3_uw = (data >> 32);
|
||||
|
||||
|
||||
AA64FpDestP0_uw = (uint32_t)data.a;
|
||||
AA64FpDestP1_uw = (data.a >> 32);
|
||||
AA64FpDestP2_uw = (uint32_t)data.b;
|
||||
AA64FpDestP3_uw = (data.b >> 32);
|
||||
'''
|
||||
elif self.flavor == "widen" or self.size == 8:
|
||||
accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));"
|
||||
else:
|
||||
accCode = "WDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));"
|
||||
if self.size == 16:
|
||||
accCode = accCode % buildMemSuffix(self.sign, 8)
|
||||
else:
|
||||
|
||||
accCode = accCode % buildMemSuffix(self.sign, self.size)
|
||||
|
||||
self.codeBlobs["memacc_code"] = accCode
|
||||
|
@ -231,6 +228,7 @@ let {{
|
|||
|
||||
# Code that actually handles the access
|
||||
if self.flavor == "fp":
|
||||
if self.size == 4:
|
||||
accCode = '''
|
||||
uint64_t data = cSwap(Mem_ud, isBigEndian64(xc->tcBase()));
|
||||
AA64FpDestP0_uw = (uint32_t)data;
|
||||
|
@ -242,6 +240,17 @@ let {{
|
|||
AA64FpDest2P2_uw = 0;
|
||||
AA64FpDest2P3_uw = 0;
|
||||
'''
|
||||
elif self.size == 8:
|
||||
accCode = '''
|
||||
AA64FpDestP0_uw = (uint32_t)Mem_tud.a;
|
||||
AA64FpDestP1_uw = (uint32_t)(Mem_tud.a >> 32);
|
||||
AA64FpDestP2_uw = 0;
|
||||
AA64FpDestP3_uw = 0;
|
||||
AA64FpDest2P0_uw = (uint32_t)Mem_tud.b;
|
||||
AA64FpDest2P1_uw = (uint32_t)(Mem_tud.b >> 32);
|
||||
AA64FpDest2P2_uw = 0;
|
||||
AA64FpDest2P3_uw = 0;
|
||||
'''
|
||||
else:
|
||||
if self.sign:
|
||||
if self.size == 4:
|
||||
|
@ -253,8 +262,8 @@ let {{
|
|||
'''
|
||||
elif self.size == 8:
|
||||
accCode = '''
|
||||
XDest = sext<64>(Mem_tud.a);
|
||||
XDest2 = sext<64>(Mem_tud.b);
|
||||
XDest = Mem_tud.a;
|
||||
XDest2 = Mem_tud.b;
|
||||
'''
|
||||
else:
|
||||
if self.size == 4:
|
||||
|
@ -416,6 +425,11 @@ let {{
|
|||
decConstBase = 'LoadStoreLitU64'
|
||||
micro = True
|
||||
|
||||
LoadImmDU64("ldp_uop", "MicroLdPairUop", 8).emit()
|
||||
LoadImmDU64("ldp_fp8_uop", "MicroLdPairFp8Uop", 8, flavor="fp").emit()
|
||||
LoadImmU64("ldfp16_uop", "MicroLdFp16Uop", 16, flavor="fp").emit()
|
||||
LoadReg64("ldfp16reg_uop", "MicroLdFp16RegUop", 16, flavor="fp").emit()
|
||||
|
||||
LoadImmDouble64("ldaxp", "LDAXPW64", 4, flavor="acexp").emit()
|
||||
LoadImmDouble64("ldaxp", "LDAXPX64", 8, flavor="acexp").emit()
|
||||
LoadImmDouble64("ldxp", "LDXPW64", 4, flavor="exp").emit()
|
||||
|
@ -428,18 +442,8 @@ let {{
|
|||
LoadRegU64("ldrfpxr_uop", "MicroLdrFpXRegUop", 8, flavor="fp").emit()
|
||||
LoadLitU64("ldrfpxl_uop", "MicroLdrFpXLitUop", 8, literal=True,
|
||||
flavor="fp").emit()
|
||||
LoadImmU64("ldrqbfpxi_uop", "MicroLdrQBFpXImmUop",
|
||||
16, flavor="fp", top = False).emit()
|
||||
LoadRegU64("ldrqbfpxr_uop", "MicroLdrQBFpXRegUop",
|
||||
16, flavor="fp", top = False).emit()
|
||||
LoadLitU64("ldrqbfpxl_uop", "MicroLdrQBFpXLitUop",
|
||||
16, literal=True, flavor="fp", top = False).emit()
|
||||
LoadImmU64("ldrqtfpxi_uop", "MicroLdrQTFpXImmUop",
|
||||
16, flavor="fp", top = True).emit()
|
||||
LoadRegU64("ldrqtfpxr_uop", "MicroLdrQTFpXRegUop",
|
||||
16, flavor="fp", top = True).emit()
|
||||
LoadLitU64("ldrqtfpxl_uop", "MicroLdrQTFpXLitUop",
|
||||
16, literal=True, flavor="fp", top = True).emit()
|
||||
LoadLitU64("ldfp16_lit__uop", "MicroLdFp16LitUop",
|
||||
16, literal=True, flavor="fp").emit()
|
||||
LoadImmDU64("ldrduxi_uop", "MicroLdrDUXImmUop", 4, sign=False).emit()
|
||||
LoadImmDU64("ldrdsxi_uop", "MicroLdrDSXImmUop", 4, sign=True).emit()
|
||||
LoadImmDU64("ldrdfpxi_uop", "MicroLdrDFpXImmUop", 4, flavor="fp").emit()
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2010-2013 ARM Limited
|
||||
// Copyright (c) 2010-2014 ARM Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// The license below extends only to copyright in the software and shall
|
||||
|
@ -55,6 +55,18 @@ let {{
|
|||
'predicate_test': predicateTest},
|
||||
['IsMicroop'])
|
||||
|
||||
microLdr2UopCode = '''
|
||||
uint64_t data = Mem_ud;
|
||||
Dest = cSwap((uint32_t) data, ((CPSR)Cpsr).e);
|
||||
Dest2 = cSwap((uint32_t) (data >> 32), ((CPSR)Cpsr).e);
|
||||
'''
|
||||
microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop',
|
||||
'MicroMemPairOp',
|
||||
{'memacc_code': microLdr2UopCode,
|
||||
'ea_code': 'EA = URb + (up ? imm : -imm);',
|
||||
'predicate_test': predicateTest},
|
||||
['IsMicroop'])
|
||||
|
||||
microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
|
||||
microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
|
||||
'MicroMemOp',
|
||||
|
@ -159,8 +171,8 @@ let {{
|
|||
|
||||
header_output = decoder_output = exec_output = ''
|
||||
|
||||
loadIops = (microLdrUopIop, microLdrRetUopIop, microLdrFpUopIop,
|
||||
microLdrDBFpUopIop, microLdrDTFpUopIop)
|
||||
loadIops = (microLdrUopIop, microLdrRetUopIop,
|
||||
microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
|
||||
storeIops = (microStrUopIop, microStrFpUopIop,
|
||||
microStrDBFpUopIop, microStrDTFpUopIop)
|
||||
for iop in loadIops + storeIops:
|
||||
|
@ -174,6 +186,12 @@ let {{
|
|||
exec_output += StoreExecute.subst(iop) + \
|
||||
StoreInitiateAcc.subst(iop) + \
|
||||
StoreCompleteAcc.subst(iop)
|
||||
|
||||
header_output += MicroMemPairDeclare.subst(microLdr2UopIop)
|
||||
decoder_output += MicroMemPairConstructor.subst(microLdr2UopIop)
|
||||
exec_output += LoadExecute.subst(microLdr2UopIop) + \
|
||||
LoadInitiateAcc.subst(microLdr2UopIop) + \
|
||||
LoadCompleteAcc.subst(microLdr2UopIop)
|
||||
}};
|
||||
|
||||
let {{
|
||||
|
|
|
@ -193,7 +193,9 @@ let {{
|
|||
return Name
|
||||
|
||||
def buildMemSuffix(sign, size):
|
||||
if size == 8:
|
||||
if size == 16:
|
||||
memSuffix = '_tud'
|
||||
elif size == 8:
|
||||
memSuffix = '_ud'
|
||||
elif size == 4:
|
||||
if sign:
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2010-2013 ARM Limited
|
||||
// Copyright (c) 2010-2014 ARM Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// The license below extends only to copyright in the software and shall
|
||||
|
@ -77,6 +77,39 @@ def template MicroMemConstructor {{
|
|||
}
|
||||
}};
|
||||
|
||||
|
||||
def template MicroMemPairDeclare {{
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
%(class_name)s(ExtMachInst machInst,
|
||||
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
|
||||
bool _up, uint8_t _imm);
|
||||
%(BasicExecDeclare)s
|
||||
%(InitiateAccDeclare)s
|
||||
%(CompleteAccDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
def template MicroMemPairConstructor {{
|
||||
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
||||
RegIndex _dreg1,
|
||||
RegIndex _dreg2,
|
||||
RegIndex _base,
|
||||
bool _up,
|
||||
uint8_t _imm)
|
||||
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
||||
_dreg1, _dreg2, _base, _up, _imm)
|
||||
{
|
||||
%(constructor)s;
|
||||
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
||||
for (int x = 0; x < _numDestRegs; x++) {
|
||||
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
||||
}
|
||||
}
|
||||
}
|
||||
}};
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Neon load/store microops
|
||||
|
|
Loading…
Reference in a new issue