diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 015f93805..00780d9c9 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -387,4 +387,40 @@ let {{
     header_output += RegRegRegOpDeclare.subst(selIop)
     decoder_output += RegRegRegOpConstructor.subst(selIop)
     exec_output += PredOpExecute.subst(selIop)
+
+    usad8Code = '''
+        uint32_t resTemp = 0;
+        for (unsigned i = 0; i < 4; i++) {
+            int low = i * 8;
+            int high = low + 7;
+            int32_t diff = bits(Op1, high, low) -
+                           bits(Op2, high, low);
+            resTemp += ((diff < 0) ? -diff : diff);
+        }
+        Dest = resTemp;
+    '''
+    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
+                             { "code": usad8Code,
+                               "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(usad8Iop)
+    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
+    exec_output += PredOpExecute.subst(usad8Iop)
+
+    usada8Code = '''
+        uint32_t resTemp = 0;
+        for (unsigned i = 0; i < 4; i++) {
+            int low = i * 8;
+            int high = low + 7;
+            int32_t diff = bits(Op1, high, low) -
+                           bits(Op2, high, low);
+            resTemp += ((diff < 0) ? -diff : diff);
+        }
+        Dest = Op3 + resTemp;
+    '''
+    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
+                              { "code": usada8Code,
+                                "predicate_test": predicateTest }, [])
+    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
+    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
+    exec_output += PredOpExecute.subst(usada8Iop)
 }};