SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
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@ -48,21 +48,13 @@ namespace SparcISA
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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#if FULL_SYSTEM
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return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
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#else
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panic("Shouldn't have a memory mapped register in SE\n");
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#endif
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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#if FULL_SYSTEM
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return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
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#else
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panic("Shouldn't have a memory mapped register in SE\n");
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#endif
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}
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@ -840,8 +840,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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#if FULL_SYSTEM
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Tick
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TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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{
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@ -1280,8 +1278,6 @@ doMmuWriteError:
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return tc->getCpuPtr()->ticks(1);
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}
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#endif
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void
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TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
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{
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@ -167,10 +167,8 @@ class TLB : public BaseTLB
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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#if FULL_SYSTEM
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Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
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Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
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#endif
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void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
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// Checkpointing
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