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SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.

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This commit is contained in:
Gabe Black 2011-10-10 00:31:51 -07:00
parent 5bab52d56d
commit 8eec565d0d
3 changed files with 0 additions and 14 deletions
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8
src/arch/sparc/mmapped_ipr.hh
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@ -48,21 +48,13 @@ namespace SparcISA
inline Tick inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt) handleIprRead(ThreadContext *xc, Packet *pkt)
{ {
#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegRead(xc, pkt); return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
#else
panic("Shouldn't have a memory mapped register in SE\n");
#endif
} }
inline Tick inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt) handleIprWrite(ThreadContext *xc, Packet *pkt)
{ {
#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
#else
panic("Shouldn't have a memory mapped register in SE\n");
#endif
} }

4
src/arch/sparc/tlb.cc
View file

@ -840,8 +840,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode); translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
} }
#if FULL_SYSTEM
Tick Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{ {
@ -1280,8 +1278,6 @@ doMmuWriteError:
return tc->getCpuPtr()->ticks(1); return tc->getCpuPtr()->ticks(1);
} }
#endif
void void
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{ {

2
src/arch/sparc/tlb.hh
View file

@ -167,10 +167,8 @@ class TLB : public BaseTLB
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc, void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode); Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
#endif
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing // Checkpointing