ARM: Make native trace print out what instruction caused an error.

src/arch/arm/nativetrace.cc

@@ -86,6 +86,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
     nState.update(this);
     mState.update(record->getThread());
 
+    bool errorFound = false;
     // Regular int regs
     for (int i = 0; i < STATE_NUMVALS; i++) {
         if (nState.changed[i] || mState.changed[i]) {
@@ -104,6 +105,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
                                       vergence, regNames[i],
                                       nState.newState[i],
                                       mState.oldState[i], mState.newState[i]);
+                errorFound = true;
             } else if (!mState.changed[i]) {
                 DPRINTF(ExecRegDelta, "%s [%5s] "\
                                       "Native: %#010x => %#010x "\
@@ -111,6 +113,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
                                       vergence, regNames[i],
                                       nState.oldState[i], nState.newState[i],
                                       mState.newState[i]);
+                errorFound = true;
             } else if (mState.oldState[i] != nState.oldState[i] ||
                        mState.newState[i] != nState.newState[i]) {
                 DPRINTF(ExecRegDelta, "%s [%5s] "\
@@ -119,9 +122,21 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
                                       vergence, regNames[i],
                                       nState.oldState[i], nState.newState[i],
                                       mState.oldState[i], mState.newState[i]);
+                errorFound = true;
             }
         }
     }
+    if (errorFound) {
+        StaticInstPtr inst = record->getStaticInst();
+        assert(inst);
+        bool ran = true;
+        if (inst->isMicroop()) {
+            ran = false;
+            inst = record->getMacroStaticInst();
+        }
+        assert(inst);
+        record->traceInst(inst, ran);
+    }
 }
 
 } /* namespace Trace */

src/cpu/NativeTrace.py

@@ -28,9 +28,9 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from ExeTracer import ExeTracer
 
-class NativeTrace(InstTracer):
+class NativeTrace(ExeTracer):
     abstract = True
     type = 'NativeTrace'
     cxx_class = 'Trace::NativeTrace'

src/cpu/nativetrace.cc

@@ -38,7 +38,7 @@ using namespace std;
 namespace Trace {
 
 NativeTrace::NativeTrace(const Params *p)
-    : InstTracer(p)
+    : ExeTracer(p)
 {
     if (ListenSocket::allDisabled())
         fatal("All listeners are disabled!");

src/cpu/nativetrace.hh

@@ -37,8 +37,8 @@
 #include "base/socket.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
+#include "cpu/exetrace.hh"
 #include "cpu/static_inst.hh"
-#include "sim/insttracer.hh"
 
 class ThreadContext;
 
@@ -46,7 +46,7 @@ namespace Trace {
 
 class NativeTrace;
 
-class NativeTraceRecord : public InstRecord
+class NativeTraceRecord : public ExeTracerRecord
 {
   protected:
     NativeTrace * parent;
@@ -56,7 +56,7 @@ class NativeTraceRecord : public InstRecord
                Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst, Addr _pc, bool spec,
                const StaticInstPtr _macroStaticInst = NULL, MicroPC _upc = 0)
-        : InstRecord(_when, _thread, _staticInst, _pc, spec,
+        : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec,
                 _macroStaticInst, _upc),
         parent(_parent)
     {
@@ -65,7 +65,7 @@ class NativeTraceRecord : public InstRecord
     void dump();
 };
 
-class NativeTrace : public InstTracer
+class NativeTrace : public ExeTracer
 {
   protected:
     int fd;