X86: Move a comment to be next to the code it describes.
--HG-- extra : convert_revision : c384391175babb7cfdd3885ae9d9f1a9405ea44f
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@ -460,6 +460,11 @@ let {{
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class Xor(LogicRegOp):
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class Xor(LogicRegOp):
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code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
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code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
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# Neither of these is quite correct because it assumes that right shifting
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# a signed or unsigned value does sign or zero extension respectively.
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# The C standard says that what happens on a right shift with a 1 in the
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# MSB position is undefined. On x86 and under likely most compilers the
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# "right thing" happens, but this isn't a guarantee.
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class Mul1s(WrRegOp):
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class Mul1s(WrRegOp):
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code = '''
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code = '''
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ProdLow = psrc1 * op2;
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ProdLow = psrc1 * op2;
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@ -489,11 +494,6 @@ let {{
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class Mulel(RdRegOp):
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class Mulel(RdRegOp):
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code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
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code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
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# Neither of these is quite correct because it assumes that right shifting
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# a signed or unsigned value does sign or zero extension respectively.
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# The C standard says that what happens on a right shift with a 1 in the
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# MSB position is undefined. On x86 and under likely most compilers the
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# "right thing" happens, but this isn't a guarantee.
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class Muleh(RdRegOp):
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class Muleh(RdRegOp):
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def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
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def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
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if not src1:
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if not src1:
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