includes: sort includes again
This commit is contained in:
parent
709d859530
commit
8d2e51c7f5
99 changed files with 217 additions and 230 deletions
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@ -37,8 +37,8 @@ namespace LittleEndianGuest {}
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#include "arch/alpha/ipr.hh"
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#include "arch/alpha/max_inst_regs.hh"
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#include "arch/alpha/types.hh"
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#include "config/full_system.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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class StaticInstPtr;
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@ -33,8 +33,8 @@
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#include "arch/alpha/types.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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class ThreadContext;
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@ -35,9 +35,9 @@
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#include "arch/arm/types.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "base/types.hh"
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class ThreadContext;
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@ -34,8 +34,8 @@
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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class ThreadContext;
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@ -36,8 +36,8 @@
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#include "arch/mips/types.hh"
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#include "arch/mips/mips_core_specific.hh"
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#include "config/full_system.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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namespace LittleEndianGuest {};
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@ -37,11 +37,8 @@
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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//XXX This is needed for size_t. We should use something other than size_t
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//#include "kern/linux/linux.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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class ThreadContext;
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@ -35,8 +35,8 @@
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#include "arch/sparc/types.hh"
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#include "arch/sparc/max_inst_regs.hh"
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#include "arch/sparc/sparc_traits.hh"
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#include "config/full_system.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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class StaticInstPtr;
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@ -33,8 +33,8 @@
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#include "arch/sparc/types.hh"
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#include "base/misc.hh"
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#include "cpu/thread_context.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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class ThreadContext;
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@ -32,6 +32,8 @@
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#ifndef __ARCH_SPARC_REGFILE_HH__
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#define __ARCH_SPARC_REGFILE_HH__
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#include <string>
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#include "arch/sparc/floatregfile.hh"
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#include "arch/sparc/intregfile.hh"
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#include "arch/sparc/isa_traits.hh"
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@ -39,8 +41,6 @@
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#include "arch/sparc/types.hh"
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#include "base/types.hh"
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#include <string>
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class Checkpoint;
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namespace SparcISA
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@ -58,12 +58,12 @@
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#ifndef __ARCH_X86_BIOS_ACPI_HH__
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#define __ARCH_X86_BIOS_ACPI_HH__
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#include <string>
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#include <vector>
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#include "base/types.hh"
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#include "sim/sim_object.hh"
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#include <vector>
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#include <string>
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class Port;
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class X86ACPIRSDPParams;
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@ -58,13 +58,13 @@
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#ifndef __ARCH_X86_BIOS_E820_HH__
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#define __ARCH_X86_BIOS_E820_HH__
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#include <vector>
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#include "base/types.hh"
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#include "params/X86E820Entry.hh"
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#include "params/X86E820Table.hh"
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#include "base/types.hh"
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#include "sim/sim_object.hh"
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#include <vector>
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class Port;
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namespace X86ISA
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@ -58,9 +58,9 @@
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#include "arch/x86/bios/intelmp.hh"
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#include "arch/x86/isa_traits.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "mem/port.hh"
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#include "sim/byteswap.hh"
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#include "base/types.hh"
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// Config entry types
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#include "params/X86IntelMPBaseConfigEntry.hh"
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@ -87,12 +87,12 @@
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#include "arch/x86/bios/smbios.hh"
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#include "arch/x86/isa_traits.hh"
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#include "base/types.hh"
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#include "mem/port.hh"
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#include "params/X86SMBiosBiosInformation.hh"
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#include "params/X86SMBiosSMBiosStructure.hh"
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#include "params/X86SMBiosSMBiosTable.hh"
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#include "sim/byteswap.hh"
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#include "base/types.hh"
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using namespace std;
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@ -91,9 +91,9 @@
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#include <string>
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#include <vector>
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#include "base/types.hh"
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#include "enums/Characteristic.hh"
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#include "enums/ExtCharacteristic.hh"
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#include "base/types.hh"
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#include "sim/sim_object.hh"
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class FunctionalPort;
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@ -33,10 +33,10 @@
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#include "arch/x86/x86_traits.hh"
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#include "base/bitunion.hh"
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#include "base/types.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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#include "base/types.hh"
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namespace X86ISA
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{
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@ -88,13 +88,13 @@
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#ifndef __ARCH_X86_MISCREGFILE_HH__
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#define __ARCH_X86_MISCREGFILE_HH__
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#include <string>
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#include "arch/x86/faults.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/types.hh"
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#include "base/types.hh"
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#include <string>
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class Checkpoint;
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namespace X86ISA
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@ -61,9 +61,9 @@
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#include <iostream>
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#include <string>
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#include "base/types.hh"
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#include "base/bitunion.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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class Checkpoint;
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@ -62,10 +62,10 @@
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/tlb.hh"
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#include "base/types.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "params/X86PagetableWalker.hh"
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#include "base/types.hh"
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class ThreadContext;
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@ -59,8 +59,8 @@
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#include "arch/x86/predecoder.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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namespace X86ISA
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{
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@ -58,6 +58,8 @@
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#ifndef __ARCH_X86_REGFILE_HH__
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#define __ARCH_X86_REGFILE_HH__
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#include <string>
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#include "arch/x86/floatregfile.hh"
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#include "arch/x86/intregfile.hh"
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#include "arch/x86/isa_traits.hh"
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#include "arch/x86/types.hh"
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#include "base/types.hh"
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#include <string>
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class Checkpoint;
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class EventManager;
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@ -61,9 +61,9 @@
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#include "arch/x86/types.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "base/types.hh"
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class ThreadContext;
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@ -58,7 +58,7 @@
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#ifndef __ARCH_X86_X86TRAITS_HH__
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#define __ARCH_X86_X86TRAITS_HH__
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#include <assert.h>
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#include <cassert>
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#include "base/types.hh"
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@ -31,19 +31,20 @@
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#ifndef __BASE__CP_ANNOTATE_HH__
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#define __BASE__CP_ANNOTATE_HH__
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#include "base/loader/symtab.hh"
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#include "config/cp_annotate.hh"
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#include "base/types.hh"
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#include "sim/serialize.hh"
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#include "sim/startup.hh"
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#include "sim/system.hh"
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#include <string>
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#include <list>
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#include <vector>
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#include <map>
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#include "base/hashmap.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "config/cp_annotate.hh"
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#include "sim/serialize.hh"
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#include "sim/startup.hh"
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#include "sim/system.hh"
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#if CP_ANNOTATE
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#include "params/CPA.hh"
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#endif
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#include <string>
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#include "base/types.hh"
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#include "base/crc.hh"
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#include "base/types.hh"
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#define ETHER_CRC_POLY_LE 0xedb88320
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#define ETHER_CRC_POLY_BE 0x04c11db6
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#include <string>
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#include "base/cprintf.hh"
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#include "base/types.hh"
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#include "base/inet.hh"
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#include "base/types.hh"
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using namespace std;
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namespace Net {
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@ -38,8 +38,8 @@
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#include <vector>
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#include "base/range.hh"
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#include "dev/etherpkt.hh"
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#include "base/types.hh"
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#include "dev/etherpkt.hh"
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#include "dnet/os.h"
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#include "dnet/eth.h"
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@ -28,10 +28,10 @@
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* Authors: Nathan Binkert
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*/
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#ifndef __INTMATH_HH__
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#define __INTMATH_HH__
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#ifndef __BASE_INTMATH_HH__
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#define __BASE_INTMATH_HH__
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#include <assert.h>
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#include <cassert>
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#include "base/types.hh"
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return 0;
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}
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#endif // __INTMATH_HH__
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#endif // __BASE_INTMATH_HH__
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@ -38,8 +38,8 @@
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "base/varargs.hh"
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#include "base/types.hh"
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#include "base/varargs.hh"
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#include "sim/core.hh"
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using namespace std;
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#include <signal.h>
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#include <unistd.h>
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#include "sim/async.hh"
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#include "base/types.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/types.hh"
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#include "sim/async.hh"
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#include "sim/core.hh"
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#include "sim/serialize.hh"
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#ifndef __RES_LIST_HH__
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#define __RES_LIST_HH__
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#include <cassert>
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#include "base/cprintf.hh"
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#include <assert.h>
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#define DEBUG_REMOVE 0
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@ -63,10 +63,10 @@
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#include "base/cprintf.hh"
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#include "base/intmath.hh"
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#include "base/refcnt.hh"
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#include "base/str.hh"
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#include "base/stats/info.hh"
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#include "base/stats/types.hh"
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#include "base/stats/visit.hh"
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#include "base/str.hh"
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#include "base/types.hh"
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class Callback;
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#include "base/stats/mysql_run.hh"
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#include "base/stats/types.hh"
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#include "base/str.hh"
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#include "base/userinfo.hh"
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#include "base/types.hh"
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#include "base/userinfo.hh"
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using namespace std;
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@ -32,8 +32,8 @@
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#include "base/statistics.hh"
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#include "base/stats/output.hh"
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#include "sim/eventq.hh"
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#include "base/types.hh"
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#include "sim/eventq.hh"
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using namespace std;
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@ -29,14 +29,14 @@
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* Nathan Binkert
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*/
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#ifndef __EXETRACE_HH__
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#define __EXETRACE_HH__
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#ifndef __CPU_EXETRACE_HH__
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#define __CPU_EXETRACE_HH__
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#include "base/trace.hh"
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#include "cpu/static_inst.hh"
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#include "base/types.hh"
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#include "sim/insttracer.hh"
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#include "cpu/static_inst.hh"
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#include "params/ExeTracer.hh"
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#include "sim/insttracer.hh"
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class ThreadContext;
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/* namespace Trace */ }
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#endif // __EXETRACE_HH__
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#endif // __CPU_EXETRACE_HH__
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "base/types.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inst_seq.hh"
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#include "base/types.hh"
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/** Struct that defines the information passed from in between stages */
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/** This information mainly goes forward through the pipeline. */
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* Authors: Korey Sewell
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*/
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#ifndef __INORDERTRACE_HH__
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#define __INORDERTRACE_HH__
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#ifndef __CPU_INORDER_INORDER_TRACE_HH__
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#define __CPU_INORDER_INORDER_TRACE_HH__
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#include "base/trace.hh"
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#include "cpu/static_inst.hh"
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#include "base/types.hh"
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#include "sim/insttracer.hh"
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#include "params/InOrderTrace.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "params/InOrderTrace.hh"
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#include "sim/insttracer.hh"
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class ThreadContext;
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namespace Trace {
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class InOrderTraceRecord : public ExeTracerRecord
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/* namespace Trace */ }
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#endif // __EXETRACE_HH__
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#endif // __CPU_INORDER_INORDER_TRACE_HH__
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@ -29,18 +29,17 @@
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* Nathan Binkert
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*/
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#ifndef __INTELTRACE_HH__
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#define __INTELTRACE_HH__
|
||||
#ifndef __CPU_INTELTRACE_HH__
|
||||
#define __CPU_INTELTRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "params/IntelTrace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class IntelTraceRecord : public InstRecord
|
||||
|
@ -85,4 +84,4 @@ class IntelTrace : public InstTracer
|
|||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __EXETRACE_HH__
|
||||
#endif // __CPU_INTELTRACE_HH__
|
||||
|
|
|
@ -29,13 +29,13 @@
|
|||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __LEGIONTRACE_HH__
|
||||
#define __LEGIONTRACE_HH__
|
||||
#ifndef __CPU_LEGIONTRACE_HH__
|
||||
#define __CPU_LEGIONTRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "params/LegionTrace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
@ -78,4 +78,4 @@ class LegionTrace : public InstTracer
|
|||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __LEGIONTRACE_HH__
|
||||
#endif // __CPU_LEGIONTRACE_HH__
|
||||
|
|
|
@ -29,19 +29,18 @@
|
|||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __NATIVETRACE_HH__
|
||||
#define __NATIVETRACE_HH__
|
||||
#ifndef __CPU_NATIVETRACE_HH__
|
||||
#define __CPU_NATIVETRACE_HH__
|
||||
|
||||
#include "base/trace.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
#include "arch/x86/intregs.hh"
|
||||
#include "arch/x86/floatregs.hh"
|
||||
#include "arch/x86/intregs.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class NativeTrace;
|
||||
|
@ -213,4 +212,4 @@ class NativeTrace : public InstTracer
|
|||
|
||||
/* namespace Trace */ }
|
||||
|
||||
#endif // __EXETRACE_HH__
|
||||
#endif // __CPU_NATIVETRACE_HH__
|
||||
|
|
|
@ -31,11 +31,11 @@
|
|||
#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
|
||||
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
|
||||
|
||||
#include "cpu/o3/sat_counter.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
#include <vector>
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "cpu/o3/sat_counter.hh"
|
||||
|
||||
/**
|
||||
* Implements a local predictor that uses the PC to index into a table of
|
||||
* counters. Note that any time a pointer to the bp_history is given, it
|
||||
|
|
|
@ -31,18 +31,16 @@
|
|||
#ifndef __CPU_O3_BPRED_UNIT_HH__
|
||||
#define __CPU_O3_BPRED_UNIT_HH__
|
||||
|
||||
#include "base/statistics.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include <list>
|
||||
|
||||
#include "base/statistics.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "cpu/o3/2bit_local_pred.hh"
|
||||
#include "cpu/o3/btb.hh"
|
||||
#include "cpu/o3/ras.hh"
|
||||
#include "cpu/o3/tournament_pred.hh"
|
||||
|
||||
#include "base/types.hh"
|
||||
|
||||
#include <list>
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
|
|
|
@ -33,9 +33,9 @@
|
|||
|
||||
#include <vector>
|
||||
|
||||
#include "sim/faults.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
// Typedef for physical register index type. Although the Impl would be the
|
||||
// most likely location for this, there are a few classes that need this
|
||||
|
|
|
@ -32,17 +32,17 @@
|
|||
#include <algorithm>
|
||||
#include <cstring>
|
||||
|
||||
#include "config/use_checker.hh"
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/utility.hh"
|
||||
#include "base/types.hh"
|
||||
#include "config/use_checker.hh"
|
||||
#include "cpu/checker/cpu.hh"
|
||||
#include "cpu/exetrace.hh"
|
||||
#include "cpu/o3/fetch.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/core.hh"
|
||||
|
||||
#if FULL_SYSTEM
|
||||
|
@ -51,8 +51,6 @@
|
|||
#include "sim/system.hh"
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
|
||||
|
|
|
@ -38,11 +38,11 @@
|
|||
|
||||
#include "base/statistics.hh"
|
||||
#include "base/timebuf.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "cpu/o3/dep_graph.hh"
|
||||
#include "cpu/op_class.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class FUPool;
|
||||
|
|
|
@ -31,9 +31,10 @@
|
|||
#ifndef __CPU_O3_RAS_HH__
|
||||
#define __CPU_O3_RAS_HH__
|
||||
|
||||
#include "base/types.hh"
|
||||
#include <vector>
|
||||
|
||||
#include "base/types.hh"
|
||||
|
||||
/** Return address stack class, implements a simple RAS. */
|
||||
class ReturnAddrStack
|
||||
{
|
||||
|
|
|
@ -36,8 +36,8 @@
|
|||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
||||
struct ltseqnum {
|
||||
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
|
||||
|
|
|
@ -31,10 +31,11 @@
|
|||
#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
|
||||
#define __CPU_O3_TOURNAMENT_PRED_HH__
|
||||
|
||||
#include "cpu/o3/sat_counter.hh"
|
||||
#include "base/types.hh"
|
||||
#include <vector>
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "cpu/o3/sat_counter.hh"
|
||||
|
||||
/**
|
||||
* Implements a tournament branch predictor, hopefully identical to the one
|
||||
* used in the 21264. It has a local predictor, which uses a local history
|
||||
|
|
|
@ -35,8 +35,8 @@
|
|||
#include <list>
|
||||
#include <utility>
|
||||
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
||||
/**
|
||||
* Simple class to hold onto a list of pairs, each pair having a memory
|
||||
|
|
|
@ -38,8 +38,8 @@
|
|||
|
||||
#include "base/statistics.hh"
|
||||
#include "base/timebuf.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
||||
class FUPool;
|
||||
class MemInterface;
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||
#define __CPU_OZONE_NULL_PREDICTOR_HH__
|
||||
|
||||
#include "cpu/inst_seq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
||||
template <class Impl>
|
||||
class NullPredictor
|
||||
|
|
|
@ -28,10 +28,10 @@
|
|||
* Authors: Steve Reinhardt
|
||||
*/
|
||||
|
||||
#include "arch/utility.hh"
|
||||
#include "arch/faults.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "arch/utility.hh"
|
||||
#include "base/cp_annotate.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/inifile.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "base/misc.hh"
|
||||
|
@ -39,6 +39,7 @@
|
|||
#include "base/range.hh"
|
||||
#include "base/stats/events.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/exetrace.hh"
|
||||
#include "cpu/profile.hh"
|
||||
|
@ -49,9 +50,9 @@
|
|||
#include "cpu/thread_context.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "params/BaseSimpleCPU.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
#include "sim/debug.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/stats.hh"
|
||||
|
@ -67,8 +68,6 @@
|
|||
#include "mem/mem_object.hh"
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#include "params/BaseSimpleCPU.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
|
|
|
@ -35,13 +35,13 @@
|
|||
#include "arch/isa_traits.hh"
|
||||
#include "arch/regfile.hh"
|
||||
#include "arch/tlb.hh"
|
||||
#include "base/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/thread_state.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
class BaseCPU;
|
||||
|
|
|
@ -36,14 +36,14 @@
|
|||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/utility.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "base/bitfield.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/refcnt.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/op_class.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
// forward declarations
|
||||
struct AlphaSimpleImpl;
|
||||
|
|
|
@ -33,12 +33,12 @@
|
|||
|
||||
#include "arch/regfile.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "base/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
// @todo: Figure out a more architecture independent way to obtain the ITB and
|
||||
// DTB pointers.
|
||||
|
|
|
@ -36,10 +36,10 @@
|
|||
#define __DEV_ALPHA_BACKDOOR_HH__
|
||||
|
||||
#include "base/range.hh"
|
||||
#include "base/types.hh"
|
||||
#include "dev/alpha/access.h"
|
||||
#include "dev/io_device.hh"
|
||||
#include "params/AlphaBackdoor.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class BaseCPU;
|
||||
|
|
|
@ -35,14 +35,14 @@
|
|||
#ifndef __DEV_ETHERLINK_HH__
|
||||
#define __DEV_ETHERLINK_HH__
|
||||
|
||||
#include "dev/etherobject.hh"
|
||||
#include "base/types.hh"
|
||||
#include "dev/etherint.hh"
|
||||
#include "dev/etherobject.hh"
|
||||
#include "dev/etherpkt.hh"
|
||||
#include "params/EtherLink.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "params/EtherLink.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class EtherDump;
|
||||
class Checkpoint;
|
||||
|
|
|
@ -36,9 +36,9 @@
|
|||
#ifndef __ETHERPKT_HH__
|
||||
#define __ETHERPKT_HH__
|
||||
|
||||
#include <cassert>
|
||||
#include <iosfwd>
|
||||
#include <memory>
|
||||
#include <assert.h>
|
||||
|
||||
#include "base/refcnt.hh"
|
||||
#include "base/types.hh"
|
||||
|
|
|
@ -37,8 +37,8 @@
|
|||
#include <iostream>
|
||||
|
||||
#include "base/bitunion.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
/** Programmable Interval Timer (Intel 8254) */
|
||||
|
|
|
@ -36,10 +36,10 @@
|
|||
#define __DEV_MIPS_BACKDOOR_HH__
|
||||
|
||||
#include "base/range.hh"
|
||||
#include "dev/mips/access.h"
|
||||
#include "dev/io_device.hh"
|
||||
#include "params/MipsBackdoor.hh"
|
||||
#include "base/types.hh"
|
||||
#include "dev/io_device.hh"
|
||||
#include "dev/mips/access.h"
|
||||
#include "params/MipsBackdoor.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class BaseCPU;
|
||||
|
|
|
@ -38,6 +38,7 @@
|
|||
|
||||
#include "base/debug.hh"
|
||||
#include "base/inet.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "dev/etherlink.hh"
|
||||
#include "dev/ns_gige.hh"
|
||||
|
@ -45,7 +46,6 @@
|
|||
#include "mem/packet.hh"
|
||||
#include "mem/packet_access.hh"
|
||||
#include "params/NSGigE.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
const char *NsRxStateStrings[] =
|
||||
|
|
|
@ -35,14 +35,14 @@
|
|||
#include "arch/vtophys.hh"
|
||||
#include "base/debug.hh"
|
||||
#include "base/inet.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/intr_control.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "dev/etherlink.hh"
|
||||
#include "dev/sinic.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/packet_access.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/stats.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#ifndef __DEV_X86_INTDEV_HH__
|
||||
#define __DEV_X86_INTDEV_HH__
|
||||
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
#include <string>
|
||||
|
||||
#include "arch/x86/x86_traits.hh"
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
|
||||
#include "dev/x86/pc.hh"
|
||||
#include "dev/x86/south_bridge.hh"
|
||||
|
|
|
@ -31,16 +31,16 @@
|
|||
#include <sys/types.h>
|
||||
#include <algorithm>
|
||||
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "kern/tru64/mbuf.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/system.hh"
|
||||
#include "sim/arguments.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/vtophys.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "kern/tru64/mbuf.hh"
|
||||
#include "sim/arguments.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
#ifndef __MBUF_HH__
|
||||
#define __MBUF_HH__
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
namespace tru64 {
|
||||
|
||||
|
|
|
@ -41,16 +41,16 @@
|
|||
#include <set>
|
||||
#include <list>
|
||||
|
||||
#include "base/range.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "base/range.hh"
|
||||
#include "base/range_map.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/port.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "params/Bus.hh"
|
||||
#include "sim/eventq.hh"
|
||||
|
||||
class Bus : public MemObject
|
||||
{
|
||||
|
|
9
src/mem/cache/cache_impl.hh
vendored
9
src/mem/cache/cache_impl.hh
vendored
|
@ -37,18 +37,15 @@
|
|||
* Cache definitions.
|
||||
*/
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "base/fast_alloc.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/range.hh"
|
||||
|
||||
#include "mem/cache/cache.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/cache/blk.hh"
|
||||
#include "mem/cache/cache.hh"
|
||||
#include "mem/cache/mshr.hh"
|
||||
#include "mem/cache/prefetch/base.hh"
|
||||
|
||||
#include "sim/sim_exit.hh" // for SimExitEvent
|
||||
|
||||
#include "sim/sim_exit.hh"
|
||||
|
||||
template<class TagStore>
|
||||
Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)
|
||||
|
|
10
src/mem/cache/mshr.cc
vendored
10
src/mem/cache/mshr.cc
vendored
|
@ -34,16 +34,16 @@
|
|||
* Miss Status and Handling Register (MSHR) definitions.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
#include <algorithm>
|
||||
|
||||
#include "mem/cache/mshr.hh"
|
||||
#include "sim/core.hh" // for curTick
|
||||
#include "base/types.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/cache/cache.hh"
|
||||
#include "mem/cache/mshr.hh"
|
||||
#include "sim/core.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
5
src/mem/cache/tags/fa_lru.cc
vendored
5
src/mem/cache/tags/fa_lru.cc
vendored
|
@ -33,13 +33,12 @@
|
|||
* Definitions a fully associative LRU tagstore.
|
||||
*/
|
||||
|
||||
#include <cassert>
|
||||
#include <sstream>
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include "mem/cache/tags/fa_lru.hh"
|
||||
#include "base/intmath.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "mem/cache/tags/fa_lru.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
10
src/mem/cache/tags/fa_lru.hh
vendored
10
src/mem/cache/tags/fa_lru.hh
vendored
|
@ -33,15 +33,15 @@
|
|||
* Declaration of a fully associative LRU tag store.
|
||||
*/
|
||||
|
||||
#ifndef __FA_LRU_HH__
|
||||
#define __FA_LRU_HH__
|
||||
#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
|
||||
#define __MEM_CACHE_TAGS_FA_LRU_HH__
|
||||
|
||||
#include <list>
|
||||
|
||||
#include "mem/cache/blk.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "mem/cache/blk.hh"
|
||||
#include "mem/cache/tags/base.hh"
|
||||
#include "mem/packet.hh"
|
||||
|
||||
/**
|
||||
* A fully associative cache block.
|
||||
|
@ -281,4 +281,4 @@ public:
|
|||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
|
||||
|
|
2
src/mem/cache/tags/iic_repl/gen.cc
vendored
2
src/mem/cache/tags/iic_repl/gen.cc
vendored
|
@ -37,10 +37,10 @@
|
|||
#include <string>
|
||||
|
||||
#include "base/misc.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/cache/tags/iic.hh"
|
||||
#include "mem/cache/tags/iic_repl/gen.hh"
|
||||
#include "params/GenRepl.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
3
src/mem/cache/tags/iic_repl/repl.hh
vendored
3
src/mem/cache/tags/iic_repl/repl.hh
vendored
|
@ -41,11 +41,10 @@
|
|||
#include <string>
|
||||
#include <list>
|
||||
|
||||
#include "cpu/smt.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/smt.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
|
||||
class IIC;
|
||||
|
||||
/**
|
||||
|
|
12
src/mem/cache/tags/lru.hh
vendored
12
src/mem/cache/tags/lru.hh
vendored
|
@ -33,16 +33,16 @@
|
|||
* Declaration of a LRU tag store.
|
||||
*/
|
||||
|
||||
#ifndef __LRU_HH__
|
||||
#define __LRU_HH__
|
||||
#ifndef __MEM_CACHE_TAGS_LRU_HH__
|
||||
#define __MEM_CACHE_TAGS_LRU_HH__
|
||||
|
||||
#include <cassert>
|
||||
#include <cstring>
|
||||
#include <list>
|
||||
|
||||
#include "mem/cache/blk.hh" // base class
|
||||
#include "mem/packet.hh" // for inlined functions
|
||||
#include <assert.h>
|
||||
#include "mem/cache/blk.hh"
|
||||
#include "mem/cache/tags/base.hh"
|
||||
#include "mem/packet.hh"
|
||||
|
||||
class BaseCache;
|
||||
|
||||
|
@ -261,4 +261,4 @@ public:
|
|||
virtual void cleanupRefs();
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif // __MEM_CACHE_TAGS_LRU_HH__
|
||||
|
|
|
@ -30,7 +30,8 @@
|
|||
* $Id$
|
||||
*/
|
||||
|
||||
#include "assert.h"
|
||||
#include <cassert>
|
||||
|
||||
#include "mem/gems_common/util.hh"
|
||||
|
||||
// Split a string into a head and tail strings on the specified
|
||||
|
|
|
@ -48,11 +48,10 @@
|
|||
#include "base/flags.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/printable.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "sim/core.hh"
|
||||
|
||||
|
||||
struct Packet;
|
||||
typedef Packet *PacketPtr;
|
||||
typedef uint8_t* PacketDataPtr;
|
||||
|
|
|
@ -33,17 +33,17 @@
|
|||
* Declaration of a non-full system Page Table.
|
||||
*/
|
||||
|
||||
#ifndef __PAGE_TABLE__
|
||||
#define __PAGE_TABLE__
|
||||
#ifndef __MEM_PAGE_TABLE_HH__
|
||||
#define __MEM_PAGE_TABLE_HH__
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "sim/faults.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/tlb.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
class Process;
|
||||
|
@ -133,4 +133,4 @@ class PageTable
|
|||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif // __MEM_PAGE_TABLE_HH__
|
||||
|
|
|
@ -42,11 +42,11 @@
|
|||
#include "arch/isa_traits.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/random.hh"
|
||||
#include "base/types.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "mem/packet_access.hh"
|
||||
#include "mem/physical.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
|
|
@ -31,13 +31,14 @@
|
|||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef DEBUG_H
|
||||
#define DEBUG_H
|
||||
#ifndef __MEM_RUBY_DEBUG_HH__
|
||||
#define __MEM_RUBY_DEBUG_HH__
|
||||
|
||||
#include <unistd.h>
|
||||
#include <iostream>
|
||||
|
||||
#include "config/ruby_debug.hh"
|
||||
#include "mem/ruby/common/Global.hh"
|
||||
|
||||
extern std::ostream * debug_cout_ptr;
|
||||
|
||||
|
@ -302,5 +303,5 @@ const bool ASSERT_FLAG = true;
|
|||
}\
|
||||
}
|
||||
|
||||
#endif //DEBUG_H
|
||||
#endif // __MEM_RUBY_DEBUG_HH__
|
||||
|
||||
|
|
|
@ -32,8 +32,8 @@
|
|||
*
|
||||
* */
|
||||
|
||||
#ifndef GLOBAL_H
|
||||
#define GLOBAL_H
|
||||
#ifndef __MEM_RUBY_GLOBAL_HH__
|
||||
#define __MEM_RUBY_GLOBAL_HH__
|
||||
|
||||
#ifdef SINGLE_LEVEL_CACHE
|
||||
const bool TWO_LEVEL_CACHE = false;
|
||||
|
@ -105,5 +105,5 @@ extern inline int max_tokens()
|
|||
}
|
||||
|
||||
|
||||
#endif //GLOBAL_H
|
||||
#endif // __MEM_RUBY_GLOBAL_HH__
|
||||
|
||||
|
|
|
@ -67,8 +67,8 @@
|
|||
* SOFTWARE.
|
||||
*------------------------------------------------------------*/
|
||||
|
||||
#include <math.h>
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
#include <cmath>
|
||||
|
||||
#include "mem/ruby/network/orion/parm_technology.hh"
|
||||
#include "mem/ruby/network/orion/SIM_port.hh"
|
||||
|
|
|
@ -26,11 +26,12 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <cassert>
|
||||
#include <cmath>
|
||||
#include <cstdio>
|
||||
|
||||
#include "mem/ruby/network/orion/parm_technology.hh"
|
||||
#include "mem/ruby/network/orion/power_utils.hh"
|
||||
#include <assert.h>
|
||||
#include <math.h>
|
||||
|
||||
/* ----------- from SIM_power_util.c ------------ */
|
||||
|
||||
|
|
|
@ -28,24 +28,20 @@
|
|||
* Authors: Daniel Sanchez
|
||||
*/
|
||||
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "mem/rubymem.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "base/output.hh"
|
||||
|
||||
// Ruby includes
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "mem/ruby/system/Sequencer.hh"
|
||||
#include "mem/ruby/init.hh"
|
||||
#include "mem/ruby/common/Debug.hh"
|
||||
|
||||
#include "sim/sim_exit.hh"
|
||||
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "base/output.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/ruby/common/Debug.hh"
|
||||
#include "mem/ruby/init.hh"
|
||||
#include "mem/ruby/system/Sequencer.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "mem/rubymem.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
|
|
|
@ -30,9 +30,7 @@
|
|||
#ifndef SLICC_GLOBAL_H
|
||||
#define SLICC_GLOBAL_H
|
||||
|
||||
#include <assert.h> /* slicc needs to include this in order to use classes in
|
||||
* ../common directory.
|
||||
*/
|
||||
#include <cassert>
|
||||
|
||||
#include "mem/gems_common/std-includes.hh"
|
||||
#include "mem/gems_common/Map.hh"
|
||||
|
|
|
@ -36,8 +36,8 @@
|
|||
|
||||
#include "base/misc.hh"
|
||||
#include "base/socket.hh"
|
||||
#include "sim/core.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/core.hh"
|
||||
#include "sim/startup.hh"
|
||||
|
||||
extern const char *compileDate;
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
%module event
|
||||
|
||||
%{
|
||||
#include "python/swig/pyevent.hh"
|
||||
#include "base/types.hh"
|
||||
#include "python/swig/pyevent.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
|
@ -75,9 +75,10 @@
|
|||
|
||||
%include "stdint.i"
|
||||
%include "std_string.i"
|
||||
|
||||
%include "base/types.hh"
|
||||
%include "sim/eventq.hh"
|
||||
%include "python/swig/pyevent.hh"
|
||||
%include "sim/eventq.hh"
|
||||
|
||||
struct CountedDrainEvent : public Event
|
||||
{
|
||||
|
|
|
@ -30,8 +30,8 @@
|
|||
|
||||
#include <Python.h>
|
||||
|
||||
#include "cpu/base.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/system.hh"
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
// import these files for SWIG to wrap
|
||||
%include "stdint.i"
|
||||
%include "std_string.i"
|
||||
|
||||
%include "base/types.hh"
|
||||
|
||||
class BaseCPU;
|
||||
|
|
|
@ -31,12 +31,12 @@
|
|||
#ifndef __SIM_ARGUMENTS_HH__
|
||||
#define __SIM_ARGUMENTS_HH__
|
||||
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
|
||||
#include "arch/vtophys.hh"
|
||||
#include "base/refcnt.hh"
|
||||
#include "mem/vport.hh"
|
||||
#include "base/types.hh"
|
||||
#include "mem/vport.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
|
|
@ -47,8 +47,8 @@
|
|||
#include "base/flags.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
class EventQueue; // forward declaration
|
||||
|
||||
|
|
|
@ -39,9 +39,9 @@
|
|||
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/async.hh"
|
||||
#include "sim/core.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/init.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
|
@ -34,9 +34,9 @@
|
|||
|
||||
#include "base/bigint.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/inst_seq.hh" // for InstSeqNum
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
|
|
@ -29,14 +29,14 @@
|
|||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
|
||||
#include "base/callback.hh"
|
||||
#include "base/inifile.hh"
|
||||
#include "base/match.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/stats/events.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/stats.hh"
|
||||
|
|
|
@ -31,13 +31,13 @@
|
|||
|
||||
#include "base/misc.hh"
|
||||
#include "base/pollevent.hh"
|
||||
#include "sim/stat_control.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/async.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "base/types.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "sim/simulate.hh"
|
||||
#include "sim/stat_control.hh"
|
||||
|
||||
/** Simulate for num_cycles additional cycles. If num_cycles is -1
|
||||
* (the default), do not limit simulation; some other event must
|
||||
|
|
|
@ -50,11 +50,11 @@
|
|||
#include <fcntl.h>
|
||||
#include <sys/uio.h>
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "base/chunk_generator.hh"
|
||||
#include "base/intmath.hh" // for RoundUp
|
||||
#include "base/misc.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "mem/translating_port.hh"
|
||||
|
|
|
@ -30,8 +30,9 @@
|
|||
|
||||
#include <iostream>
|
||||
#include <cassert>
|
||||
#include "base/types.hh"
|
||||
|
||||
#include "base/range_map.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
|
@ -31,8 +31,8 @@
|
|||
#include <cassert>
|
||||
#include <iostream>
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "base/range_map.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#include <sys/user.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/ptrace.h>
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
#include <string>
|
||||
|
||||
#include "tracechild.hh"
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#include <linux/user.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/ptrace.h>
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
#include <string>
|
||||
|
||||
#include "tracechild.hh"
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
#define TRACECHILD_SPARC_HH
|
||||
|
||||
#include <asm-sparc64/reg.h>
|
||||
#include <assert.h>
|
||||
#include <cassert>
|
||||
#include <ostream>
|
||||
#include <stdint.h>
|
||||
#include <string>
|
||||
|
|
Loading…
Reference in a new issue