Changed the getReg and setReg functions so that they work like netbsd. Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented.
--HG-- extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179
This commit is contained in:
Gabe Black
parent
f1a55570d3
commit
8cb7ac0900
2 changed files with 20 additions and 104 deletions
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@ -149,46 +149,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
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bool
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RemoteGDB::acc(Addr va, size_t len)
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{
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#if 0
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Addr last_va;
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va = TheISA::TruncPage(va);
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last_va = TheISA::RoundPage(va + len);
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do {
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if (TheISA::IsK0Seg(va)) {
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if (va < (TheISA::K0SegBase + pmem->size())) {
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DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
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"%#x < K0SEG + size\n", va);
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return true;
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} else {
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DPRINTF(GDBAcc, "acc: Mapping invalid %#x > K0SEG + size\n",
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va);
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return false;
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}
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}
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/**
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* This code says that all accesses to palcode (instruction and data)
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* are valid since there isn't a va->pa mapping because palcode is
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* accessed physically. At some point this should probably be cleaned up
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* but there is no easy way to do it.
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*/
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if (AlphaISA::PcPAL(va) || va < 0x10000)
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return true;
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Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20);
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TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va);
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if (!pte.valid()) {
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DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
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return false;
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}
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va += TheISA::PageBytes;
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} while (va < last_va);
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DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
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#endif
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//@Todo In NetBSD, this function checks if all addresses
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//from va to va + len have valid page mape entries. Not
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//sure how this will work for other OSes or in general.
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return true;
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}
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@ -204,12 +167,11 @@ RemoteGDB::getregs()
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gdbregs.regs[RegPc] = context->readPC();
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gdbregs.regs[RegNpc] = context->readNextPC();
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for(int x = RegG0; x <= RegI7; x++)
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for(int x = RegG0; x <= RegI0 + 7; x++)
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gdbregs.regs[x] = context->readIntReg(x - RegG0);
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for(int x = RegF0; x <= RegF31; x++)
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gdbregs.regs[x] = context->readFloatRegBits(x - RegF0);
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gdbregs.regs[RegY] = context->readMiscReg(MISCREG_Y);
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//XXX need to also load up Psr, Wim, Tbr, Fpsr, and Cpsr
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//Floating point registers are left at 0 in netbsd
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//All registers other than the pc, npc and int regs
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//are ignored as well.
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}
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///////////////////////////////////////////////////////////
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@ -223,56 +185,19 @@ RemoteGDB::setregs()
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{
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context->setPC(gdbregs.regs[RegPc]);
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context->setNextPC(gdbregs.regs[RegNpc]);
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for(int x = RegG0; x <= RegI7; x++)
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for(int x = RegG0; x <= RegI0 + 7; x++)
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context->setIntReg(x - RegG0, gdbregs.regs[x]);
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for(int x = RegF0; x <= RegF31; x++)
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context->setFloatRegBits(x - RegF0, gdbregs.regs[x]);
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context->setMiscRegWithEffect(MISCREG_Y, gdbregs.regs[RegY]);
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//XXX need to also set Psr, Wim, Tbr, Fpsr, and Cpsr
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//Only the integer registers, pc and npc are set in netbsd
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}
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void
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RemoteGDB::clearSingleStep()
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{
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#if 0
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DPRINTF(GDBMisc, "clearSingleStep bt_addr=%#x nt_addr=%#x\n",
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takenBkpt.address, notTakenBkpt.address);
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if (takenBkpt.address != 0)
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clearTempBreakpoint(takenBkpt);
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if (notTakenBkpt.address != 0)
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clearTempBreakpoint(notTakenBkpt);
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#endif
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panic("SPARC does not support hardware single stepping\n");
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}
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void
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RemoteGDB::setSingleStep()
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{
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#if 0
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Addr pc = context->readPC();
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Addr npc, bpc;
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bool set_bt = false;
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npc = pc + sizeof(MachInst);
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// User was stopped at pc, e.g. the instruction at pc was not
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// executed.
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MachInst inst = read<MachInst>(pc);
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StaticInstPtr si(inst);
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if (si->hasBranchTarget(pc, context, bpc)) {
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// Don't bother setting a breakpoint on the taken branch if it
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// is the same as the next pc
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if (bpc != npc)
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set_bt = true;
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}
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DPRINTF(GDBMisc, "setSingleStep bt_addr=%#x nt_addr=%#x\n",
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takenBkpt.address, notTakenBkpt.address);
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setTempBreakpoint(notTakenBkpt, npc);
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if (set_bt)
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setTempBreakpoint(takenBkpt, bpc);
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#endif
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panic("SPARC does not support hardware single stepping\n");
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}
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@ -49,22 +49,15 @@ namespace SparcISA
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protected:
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enum RegisterConstants
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{
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RegG0, RegG1, RegG2, RegG3, RegG4, RegG5, RegG6, RegG7,
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RegO0, RegO1, RegO2, RegO3, RegO4, RegO5, RegO6, RegO7,
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RegL0, RegL1, RegL2, RegL3, RegL4, RegL5, RegL6, RegL7,
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RegI0, RegI1, RegI2, RegI3, RegI4, RegI5, RegI6, RegI7,
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RegF0, RegF1, RegF2, RegF3, RegF4, RegF5, RegF6, RegF7,
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RegF8, RegF9, RegF10, RegF11, RegF12, RegF13, RegF14, RegF15,
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RegF16, RegF17, RegF18, RegF19, RegF20, RegF21, RegF22, RegF23,
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RegF24, RegF25, RegF26, RegF27, RegF28, RegF29, RegF30, RegF31,
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RegY,
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RegPsr,
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RegWim,
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RegTbr,
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RegPc,
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RegNpc,
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RegFpsr,
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RegCpsr,
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RegG0 = 0, RegO0 = 8, RegL0 = 16, RegI0 = 24,
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RegF0 = 32, RegF32 = 64,
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RegPc = 80, RegNpc, RegCcr, RegFsr, RegFprs, RegY, RegAsi,
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RegVer, RegTick, RegPil, RegPstate,
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RegTstate, RegTba, RegTl, RegTt, RegTpc, RegTnpc, RegWstate,
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RegCwp, RegCansave, RegCanrestore, RegCleanwin, RegOtherwin,
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RegAsr16 = 103,
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RegIcc = 119, RegXcc,
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RegFcc0 = 121,
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NumGDBRegs
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};
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@ -79,8 +72,6 @@ namespace SparcISA
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void clearSingleStep();
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void setSingleStep();
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Addr singleStepBreaks[2];
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};
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}
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