mem: Simplify DRAM response scheduling
This patch simplifies the DRAM response scheduling based on the assumption that they are always returned in order.
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8e3869411d
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8c56efe747
2 changed files with 20 additions and 54 deletions
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@ -1041,47 +1041,6 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
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}
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}
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}
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}
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void
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DRAMCtrl::moveToRespQ()
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{
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// Remove from read queue
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DRAMPacket* dram_pkt = readQueue.front();
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readQueue.pop_front();
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// sanity check
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assert(dram_pkt->size <= burstSize);
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// Insert into response queue sorted by readyTime
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// It will be sent back to the requestor at its
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// readyTime
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if (respQueue.empty()) {
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respQueue.push_front(dram_pkt);
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assert(!respondEvent.scheduled());
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assert(dram_pkt->readyTime >= curTick());
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schedule(respondEvent, dram_pkt->readyTime);
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} else {
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bool done = false;
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auto i = respQueue.begin();
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while (!done && i != respQueue.end()) {
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if ((*i)->readyTime > dram_pkt->readyTime) {
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respQueue.insert(i, dram_pkt);
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done = true;
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}
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++i;
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}
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if (!done)
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respQueue.push_back(dram_pkt);
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assert(respondEvent.scheduled());
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if (respQueue.front()->readyTime < respondEvent.when()) {
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assert(respQueue.front()->readyTime >= curTick());
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reschedule(respondEvent, respQueue.front()->readyTime);
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}
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}
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}
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void
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void
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DRAMCtrl::processNextReqEvent()
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DRAMCtrl::processNextReqEvent()
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{
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{
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@ -1152,13 +1111,28 @@ DRAMCtrl::processNextReqEvent()
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// front of the read queue
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// front of the read queue
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chooseNext(readQueue);
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chooseNext(readQueue);
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doDRAMAccess(readQueue.front());
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DRAMPacket* dram_pkt = readQueue.front();
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doDRAMAccess(dram_pkt);
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// At this point we're done dealing with the request
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// At this point we're done dealing with the request
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// It will be moved to a separate response queue with a
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readQueue.pop_front();
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// correct readyTime, and eventually be sent back at that
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// time
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// sanity check
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moveToRespQ();
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assert(dram_pkt->size <= burstSize);
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assert(dram_pkt->readyTime >= curTick());
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// Insert into response queue. It will be sent back to the
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// requestor at its readyTime
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if (respQueue.empty()) {
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assert(!respondEvent.scheduled());
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schedule(respondEvent, dram_pkt->readyTime);
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} else {
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assert(respQueue.back()->readyTime <= dram_pkt->readyTime);
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assert(respondEvent.scheduled());
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}
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respQueue.push_back(dram_pkt);
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// we have so many writes that we have to transition
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// we have so many writes that we have to transition
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if (writeQueue.size() > writeHighThreshold) {
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if (writeQueue.size() > writeHighThreshold) {
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@ -366,14 +366,6 @@ class DRAMCtrl : public AbstractMemory
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*/
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*/
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void chooseNext(std::deque<DRAMPacket*>& queue);
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void chooseNext(std::deque<DRAMPacket*>& queue);
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/**
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* Move the request at the head of the read queue to the response
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* queue, sorting by readyTime.\ If it is the only packet in the
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* response queue, schedule a respond event to send it back to the
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* outside world
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*/
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void moveToRespQ();
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/**
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/**
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* For FR-FCFS policy reorder the read/write queue depending on row buffer
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* For FR-FCFS policy reorder the read/write queue depending on row buffer
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* hits and earliest banks available in DRAM
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* hits and earliest banks available in DRAM
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