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x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.

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There was already a stub device at 0x80, the port traditionally used for an IO
delay. 0x80 is also the port used for POST codes sent by firmware, and that
may have prompted adding this port as a second option.
This commit is contained in:
Gabe Black 2014-11-21 17:22:02 -08:00
parent 708e80d9bb
commit 8bbfb1b39d
1 changed files with 5 additions and 3 deletions
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8
src/dev/x86/Pc.py
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@ -49,8 +49,9 @@ class Pc(Platform):
south_bridge = SouthBridge() south_bridge = SouthBridge()
# "Non-existant" port used for timing purposes by the linux kernel # "Non-existant" ports used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything, # Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway. # but the linux kernel fiddles with them anway.
@ -71,7 +72,8 @@ class Pc(Platform):
def attachIO(self, bus, dma_ports = []): def attachIO(self, bus, dma_ports = []):
self.south_bridge.attachIO(bus, dma_ports) self.south_bridge.attachIO(bus, dma_ports)
self.i_dont_exist.pio = bus.master self.i_dont_exist1.pio = bus.master
self.i_dont_exist2.pio = bus.master
self.behind_pci.pio = bus.master self.behind_pci.pio = bus.master
self.com_1.pio = bus.master self.com_1.pio = bus.master
self.fake_com_2.pio = bus.master self.fake_com_2.pio = bus.master