Fix up bus draining and add draining to the caches.
src/mem/bus.cc: Fix up draining to work properly. src/mem/bus.hh: Initialize drainEvent to NULL. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Add draining to the caches. --HG-- extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
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244e0c884c
commit
8ba73da056
4 changed files with 61 additions and 8 deletions
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@ -240,10 +240,10 @@ Bus::recvRetry(int id)
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busIdle.reschedule(tickNextIdle);
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}
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}
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}
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//If we weren't able to drain before, we might be able to now.
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if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle)
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drainEvent->process();
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}
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}
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Port *
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@ -521,10 +521,10 @@ Bus::drain(Event * de)
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//waiting. We might be idle but have someone waiting if the device we
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//contacted for a retry didn't actually retry.
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if (curTick >= tickNextIdle && retryList.size() == 0) {
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return 0;
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} else {
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drainEvent = de;
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return 1;
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} else {
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return 0;
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}
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}
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@ -257,8 +257,8 @@ class Bus : public MemObject
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Bus(const std::string &n, int bus_id, int _clock, int _width,
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bool responder_set)
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: MemObject(n), busId(bus_id), clock(_clock), width(_width),
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tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
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responderSet(responder_set)
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tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
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defaultPort(NULL), responderSet(responder_set)
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{
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//Both the width and clock period must be positive
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if (width <= 0)
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22
src/mem/cache/base_cache.cc
vendored
22
src/mem/cache/base_cache.cc
vendored
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@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry()
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}
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waitingOnRetry = false;
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}
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// Check if we're done draining once this list is empty
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if (drainList.empty())
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cache->checkDrain();
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}
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else if (!isCpuSide)
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{
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@ -338,6 +341,10 @@ BaseCache::CacheEvent::process()
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cachePort->drainList.push_back(pkt);
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cachePort->waitingOnRetry = true;
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}
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// Check if we're done draining once this list is empty
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if (cachePort->drainList.empty())
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cachePort->cache->checkDrain();
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}
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const char *
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@ -599,3 +606,18 @@ BaseCache::regStats()
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;
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}
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unsigned int
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BaseCache::drain(Event *de)
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{
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// Set status
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if (!canDrain()) {
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drainEvent = de;
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changeState(SimObject::Draining);
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return 1;
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}
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changeState(SimObject::Drained);
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return 0;
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}
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33
src/mem/cache/base_cache.hh
vendored
33
src/mem/cache/base_cache.hh
vendored
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@ -105,6 +105,8 @@ class BaseCache : public MemObject
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void clearBlocked();
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bool canDrain() { return drainList.empty(); }
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bool blocked;
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bool mustSendRetry;
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@ -227,6 +229,9 @@ class BaseCache : public MemObject
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/** The number of misses to trigger an exit event. */
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Counter missCount;
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/** The drain event. */
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Event *drainEvent;
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public:
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// Statistics
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/**
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@ -340,7 +345,7 @@ class BaseCache : public MemObject
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BaseCache(const std::string &name, Params ¶ms)
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: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
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slaveRequests(0), blkSize(params.blkSize),
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missCount(params.maxMisses)
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missCount(params.maxMisses), drainEvent(NULL)
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{
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//Start ports at null if more than one is created we should panic
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cpuSidePort = NULL;
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@ -477,6 +482,7 @@ class BaseCache : public MemObject
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{
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uint8_t flag = 1<<cause;
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masterRequests &= ~flag;
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checkDrain();
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}
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/**
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@ -512,6 +518,7 @@ class BaseCache : public MemObject
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{
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uint8_t flag = 1<<cause;
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slaveRequests &= ~flag;
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checkDrain();
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}
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/**
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@ -589,6 +596,30 @@ class BaseCache : public MemObject
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return;
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}
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}
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virtual unsigned int drain(Event *de);
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void checkDrain()
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{
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if (drainEvent && canDrain()) {
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drainEvent->process();
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changeState(SimObject::Drained);
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// Clear the drain event
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drainEvent = NULL;
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}
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}
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bool canDrain()
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{
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if (doMasterRequest() || doSlaveRequest()) {
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return false;
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} else if (memSidePort && !memSidePort->canDrain()) {
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return false;
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} else if (cpuSidePort && !cpuSidePort->canDrain()) {
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return false;
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}
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return true;
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}
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};
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#endif //__BASE_CACHE_HH__
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