sparc files that were removed from revision 1.888
--HG-- extra : convert_revision : f285a442b64eee183f7d0f6c203f0b0aa7ea8586
This commit is contained in:
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0162c52f17
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82
arch/sparc/isa_desc/base.h
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82
arch/sparc/isa_desc/base.h
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@ -0,0 +1,82 @@
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////////////////////////////////////////////////////////////////////
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//
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// Base class for sparc instructions, and some support functions
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//
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output header {{
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/**
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* Base class for all SPARC static instructions.
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*/
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class SparcStaticInst : public StaticInst<SPARCISA>
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{
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protected:
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// Constructor.
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SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
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: StaticInst<SPARCISA>(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition);
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}};
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output decoder {{
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std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if(_numSrcRegs > 0)
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{
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1)
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{
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if(_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition)
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{
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switch(condition)
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{
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case 0b1000: return true;
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case 0b0000: return false;
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case 0b1001: return !codes.z;
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case 0b0001: return codes.z;
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case 0b1010: return !(codes.z | (codes.n ^ codes.v));
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case 0b0010: return codes.z | (codes.n ^ codes.v);
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case 0b1011: return !(codes.n ^ codes.v);
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case 0b0011: return (codes.n ^ codes.v);
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case 0b1100: return !(codes.c | codes.z);
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case 0b0100: return (codes.c | codes.z);
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case 0b1101: return !codes.c;
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case 0b0101: return codes.c;
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case 0b1110: return !codes.n;
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case 0b0110: return codes.n;
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case 0b1111: return !codes.v;
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case 0b0111: return codes.v;
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}
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}
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}};
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50
arch/sparc/isa_desc/bitfields.h
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50
arch/sparc/isa_desc/bitfields.h
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@ -0,0 +1,50 @@
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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// Bitfields are shared liberally between instruction formats, so they are
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// simply defined alphabetically
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def bitfield A <29>;
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def bitfield CC02 <20>;
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def bitfield CC03 <25>;
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def bitfield CC04 <11>;
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def bitfield CC12 <21>;
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def bitfield CC13 <26>;
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def bitfield CC14 <12>;
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def bitfield CC2 <18>;
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def bitfield CMASK <6:4>;
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def bitfield COND2 <28:25>;
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def bitfield COND4 <17:14>;
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def bitfield D16HI <21:20>;
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def bitfield D16LO <13:0>;
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def bitfield DISP19 <18:0>;
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def bitfield DISP22 <21:0>;
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def bitfield DISP30 <29:0>;
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def bitfield FCN <29:26>;
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def bitfield I <13>;
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def bitfield IMM_ASI <12:5>;
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def bitfield IMM22 <21:0>;
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def bitfield MMASK <3:0>;
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def bitfield OP <31:30>;
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def bitfield OP2 <24:22>;
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def bitfield OP3 <24:19>;
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def bitfield OPF <13:5>;
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def bitfield OPF_CC <13:11>;
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def bitfield OPF_LOW5 <9:5>;
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def bitfield OPF_LOW6 <10:5>;
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def bitfield P <19>;
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def bitfield RCOND2 <27:25>;
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def bitfield RCOND3 <12:10>;
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def bitfield RCOND4 <12:10>;
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def bitfield RD <29:25>;
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def bitfield RS1 <18:14>;
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def bitfield RS2 <4:0>;
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def bitfield SHCNT32 <4:0>;
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def bitfield SHCNT64 <5:0>;
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def bitfield SIMM10 <9:0>;
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def bitfield SIMM11 <10:0>;
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def bitfield SIMM13 <12:0>;
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def bitfield SW_TRAP <6:0>;
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def bitfield X <12>;
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638
arch/sparc/isa_desc/decoder.h
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638
arch/sparc/isa_desc/decoder.h
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@ -0,0 +1,638 @@
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////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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decode OP default Trap::unknown({{illegal_instruction}}) {
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0x0: decode OP2 {
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0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
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0x1: Branch::bpcc({{
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switch((CC12 << 1) | CC02)
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{
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case 1: case 3:
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throw illegal_instruction;
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case 0:
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if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
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;//branchHere
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break;
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case 2:
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if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
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;//branchHere
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break;
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}
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}});//BPcc
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0x2: Branch::bicc({{
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if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
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;//branchHere
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}});//Bicc
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0x3: Branch::bpr({{
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switch(RCOND)
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{
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case 0: case 4:
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throw illegal_instruction;
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case 1:
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if(Rs1 == 0) ;//branchHere
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break;
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case 2:
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if(Rs1 <= 0) ;//branchHere
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break;
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case 3:
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if(Rs1 < 0) ;//branchHere
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break;
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case 5:
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if(Rs1 != 0) ;//branchHere
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break;
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case 6:
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if(Rs1 > 0) ;//branchHere
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break;
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case 7:
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if(Rs1 >= 0) ;//branchHere
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break;
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}
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}}); //BPr
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0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); //SETHI (or NOP if rd == 0 and imm == 0)
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0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
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0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc
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}
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0x1: Branch::call({{
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//branch here
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Rd = xc->pc;
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}});
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0x2: decode OP3 {
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format IntegerOp {
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0x00: add({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
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Rd = Rs1.sdw + val2;
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}});//ADD
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0x01: and({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & val2;
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}});//AND
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0x02: or({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | val2;
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}});//OR
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0x03: xor({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw ^ val2;
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}});//XOR
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0x04: sub({{
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INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1;
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Rd = Rs1.sdw + val2;
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}});//SUB
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0x05: andn({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & ~val2;
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}});//ANDN
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0x06: orn({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | ~val2;
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}});//ORN
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0x07: xnor({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = ~(Rs1.udw ^ val2);
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}});//XNOR
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0x08: addc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
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INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd = Rs1.sdw + val2 + carryin;
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}});//ADDC
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0x09: mulx({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 * val2;
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}});//MULX
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0x0A: umul({{
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UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
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}});//UMUL
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0x0B: smul({{
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INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
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rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
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}});//SMUL
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0x0C: subc({{
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INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1;
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INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd.sdw = Rs1.sdw + val2 + carryin;
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}});//SUBC
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0x0D: udivx({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) throw division_by_zero;
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Rd.udw = Rs1.udw / val2;
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}});//UDIVX
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0x0E: udiv({{
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UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0) throw division_by_zero;
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resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
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INT32 overflow = (resTemp<63:32> != 0);
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if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
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else rd.udw = resTemp;
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}}); //UDIV
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0x0F: sdiv({{
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INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0) throw division_by_zero;
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Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
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INT32 overflow = (resTemp<63:31> != 0);
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INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
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else rd.udw = resTemp;
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}});//SDIV
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}
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format IntegerOpCc {
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0x10: addcc({{
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INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDcc
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0x11: andcc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & val2;}}
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,{{0}},{{0}},{{0}},{{0}});//ANDcc
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0x12: orcc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | val2;}}
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,{{0}},{{0}},{{0}},{{0}});//ORcc
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0x13: xorcc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 ^ val2;}}
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,{{0}},{{0}},{{0}},{{0}});//XORcc
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0x14: subcc({{
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INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 - val2;}},
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{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBcc
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0x15: andncc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & ~val2;}}
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,{{0}},{{0}},{{0}},{{0}});//ANDNcc
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0x16: orncc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | ~val2;}}
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,{{0}},{{0}},{{0}},{{0}});//ORNcc
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0x17: xnorcc({{
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INT64 val2 = (I ? SIMM13.sdw : Rs2);
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Rd = ~(Rs1 ^ val2);}}
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,{{0}},{{0}},{{0}},{{0}});//XNORcc
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0x18: addccc({{
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INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDCcc
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0x1A: umulcc({{
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UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
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,{{0}},{{0}},{{0}},{{0}});//UMULcc
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0x1B: smulcc({{
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INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
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,{{0}},{{0}},{{0}},{{0}});//SMULcc
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0x1C: subccc({{
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INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
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INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
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Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
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{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBCcc
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0x1D: udivxcc({{
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UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) throw division_by_zero;
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Rd.udw = Rs1.udw / val2;}}
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,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
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0x1E: udivcc({{
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UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0) throw division_by_zero;
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resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
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INT32 overflow = (resTemp<63:32> != 0);
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if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
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else rd.udw = resTemp;}},
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{{0}},
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{{overflow}},
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{{0}},
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{{0}}
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);//UDIVcc
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0x1F: sdivcc({{
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INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0) throw division_by_zero;
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Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
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INT32 overflow = (resTemp<63:31> != 0);
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INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
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else rd.udw = resTemp;}},
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{{0}},
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{{overflow || underflow}},
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{{0}},
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{{0}}
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);//SDIVcc
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0x20: taddcc({{
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INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;
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INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TADDcc
|
||||
0x21: tsubcc({{
|
||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
||||
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||
{{overflow}},
|
||||
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TSUBcc
|
||||
0x22: taddcctv({{
|
||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||
if(overflow) throw tag_overflow;}},
|
||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||
{{overflow}},
|
||||
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TADDccTV
|
||||
0x23: tsubcctv({{
|
||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||
Rd = resTemp = Rs1 + val2;
|
||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||
if(overflow) throw tag_overflow;}},
|
||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||
{{overflow}},
|
||||
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||
);//TSUBccTV
|
||||
0x24: mulscc({{
|
||||
INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
|
||||
INT32 multiplier = Rs1<31:0>;
|
||||
INT32 savedLSB = Rs1<0:>;
|
||||
multiplier = multipler<31:1> |
|
||||
((xc->regs.MiscRegs.ccrFields.iccFields.n
|
||||
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
|
||||
if(!xc->regs.MiscRegs.yFields.value<0:>)
|
||||
multiplicand = 0;
|
||||
Rd = resTemp = multiplicand + multiplier;
|
||||
xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
|
||||
{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
|
||||
{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
|
||||
{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
|
||||
{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
|
||||
);//MULScc
|
||||
}
|
||||
format IntegerOp
|
||||
{
|
||||
0x25: decode X {
|
||||
0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
|
||||
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
|
||||
}
|
||||
0x26: decode X {
|
||||
0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
|
||||
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
|
||||
}
|
||||
0x27: decode X {
|
||||
0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
|
||||
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
|
||||
}
|
||||
0x28: decode RS1 {
|
||||
0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
|
||||
0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
|
||||
0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
|
||||
0x4: rdtick({{
|
||||
if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
|
||||
xc->regs.MiscRegs.tickFields.npt == 1)
|
||||
throw privileged_action;
|
||||
Rd = xc->regs.MiscRegs.tick;
|
||||
}});//RDTICK
|
||||
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
|
||||
0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
|
||||
0xF: decode I {
|
||||
0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
|
||||
0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
|
||||
}
|
||||
}
|
||||
|
||||
0x2A: decode RS1 {
|
||||
0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
|
||||
0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
|
||||
0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
|
||||
0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
|
||||
0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
|
||||
0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
|
||||
0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
|
||||
0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
|
||||
0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
|
||||
0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
|
||||
0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
|
||||
0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
|
||||
0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
|
||||
0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
|
||||
0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
|
||||
0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
|
||||
}
|
||||
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
|
||||
0x2C: movcc({{
|
||||
ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
|
||||
switch(ccBank)
|
||||
{
|
||||
case 0: case 1: case 2: case 3:
|
||||
throw fp_disabled;
|
||||
break;
|
||||
case 5: case 7:
|
||||
throw illegal_instruction;
|
||||
break;
|
||||
case 4:
|
||||
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
|
||||
Rd = (I ? SIMM11.sdw : RS2);
|
||||
break;
|
||||
case 6:
|
||||
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
|
||||
Rd = (I ? SIMM11.sdw : RS2);
|
||||
break;
|
||||
}
|
||||
}});//MOVcc
|
||||
0x2D: sdivx({{
|
||||
INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
if(val2 == 0) throw division_by_zero;
|
||||
Rd.sdw = Rs1.sdw / val2;
|
||||
}});//SDIVX
|
||||
0x2E: decode RS1 {
|
||||
0x0: IntegerOp::popc({{
|
||||
INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
||||
for(unsigned int x = 0; x < 16; x++)
|
||||
{
|
||||
count += oneBits[val2 & 0xF];
|
||||
val2 >> 4;
|
||||
}
|
||||
}});//POPC
|
||||
}
|
||||
0x2F: movr({{
|
||||
UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
||||
switch(RCOND)
|
||||
{
|
||||
case 0: case 4:
|
||||
throw illegal_instruction;
|
||||
break;
|
||||
case 1:
|
||||
if(Rs1 == 0) Rd = val2;
|
||||
break;
|
||||
case 2:
|
||||
if(Rs1 <= 0) Rd = val2;
|
||||
break;
|
||||
case 3:
|
||||
if(Rs1 = 0) Rd = val2;
|
||||
break;
|
||||
case 5:
|
||||
if(Rs1 != 0) Rd = val2;
|
||||
break;
|
||||
case 6:
|
||||
if(Rs1 > 0) Rd = val2;
|
||||
break;
|
||||
case 7:
|
||||
if(Rs1 >= 0) Rd = val2;
|
||||
break;
|
||||
}
|
||||
}});//MOVR
|
||||
0x30: decode RD {
|
||||
0x0: wry({{
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.y = Rs1 ^ val2;
|
||||
}});//WRY
|
||||
0x2: wrccr({{
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.ccr = Rs1 ^ val2;
|
||||
}});//WRCCR
|
||||
0x3: wrasi({{
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
||||
}});//WRASI
|
||||
0x6: wrfprs({{
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
||||
}});//WRFPRS
|
||||
0xF: Trap::sir({{software_initiated_reset}}); //SIR
|
||||
}
|
||||
0x31: decode FCN {
|
||||
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
|
||||
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
|
||||
}
|
||||
0x32: decode RD {
|
||||
0x0: wrprtpc({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||
}});
|
||||
0x1: wrprtnpc({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||
}});
|
||||
0x2: wrprtstate({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||
}});
|
||||
0x3: wrprtt({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||
}});
|
||||
0x4: wrprtick({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tick = Rs1 ^ val2;
|
||||
}});
|
||||
0x5: wrprtba({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tba = Rs1 ^ val2;
|
||||
}});
|
||||
0x6: wrprpstate({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
|
||||
}});
|
||||
0x7: wrprtl({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.tl = Rs1 ^ val2;
|
||||
}});
|
||||
0x8: wrprpil({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.pil = Rs1 ^ val2;
|
||||
}});
|
||||
0x9: wrprcwp({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
|
||||
}});
|
||||
0xA: wrprcansave({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
|
||||
}});
|
||||
0xB: wrprcanrestore({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
|
||||
}});
|
||||
0xC: wrprcleanwin({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
|
||||
}});
|
||||
0xD: wrprotherwin({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
|
||||
}});
|
||||
0xE: wrprwstate({{checkPriv
|
||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
|
||||
}});
|
||||
}
|
||||
|
||||
0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
|
||||
0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
|
||||
|
||||
|
||||
0x38: Branch::jmpl({{//Stuff}}); //JMPL
|
||||
0x39: Branch::return({{//Other Stuff}}); //RETURN
|
||||
0x3A: Trap::tcc({{
|
||||
switch((CC14 << 1) | (CC04 << 0))
|
||||
{
|
||||
case 1: case 3:
|
||||
throw illegal_instruction;
|
||||
case 0:
|
||||
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
|
||||
throw trap_instruction;
|
||||
break;
|
||||
case 2:
|
||||
if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
|
||||
throw trap_instruction;
|
||||
break;
|
||||
}
|
||||
}}); //Tcc
|
||||
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
|
||||
0x3C: BasicOperate::save({{//leprechauns); //SAVE
|
||||
0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
|
||||
0x3E: decode FCN {
|
||||
0x1: BasicOperate::done({{//Done thing}}); //DONE
|
||||
0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
|
||||
}
|
||||
}
|
||||
}
|
||||
0x3: decode OP3 {
|
||||
format Mem {
|
||||
0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
|
||||
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
|
||||
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
|
||||
0x03: ldd({{
|
||||
UINT64 val = Mem.udw;
|
||||
setIntReg(RD & (~1), val<31:0>);
|
||||
setIntReg(RD | 1, val<63:32>);
|
||||
}});//LDD
|
||||
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
|
||||
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
|
||||
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
|
||||
0x07: std({{
|
||||
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
||||
}});//STD
|
||||
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
|
||||
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
|
||||
0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
|
||||
0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
|
||||
|
||||
0x0D: ldstub({{
|
||||
Rd.ub = Mem.ub;
|
||||
Mem.ub = 0xFF;
|
||||
}}); //LDSTUB
|
||||
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
|
||||
0x0F: swap({{
|
||||
UINT32 temp = Rd.uw;
|
||||
Rd.uw = Mem.uw;
|
||||
Mem.uw = temp;
|
||||
}}); //SWAP
|
||||
0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
|
||||
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
|
||||
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
|
||||
0x13: ldda({{
|
||||
UINT64 val = Mem.udw;
|
||||
setIntReg(RD & (~1), val<31:0>);
|
||||
setIntReg(RD | 1, val<63:32>);
|
||||
}}); //LDDA
|
||||
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
|
||||
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
|
||||
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
|
||||
0x17: stda({{
|
||||
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
||||
}}); //STDA
|
||||
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
|
||||
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
|
||||
0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
|
||||
0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
|
||||
|
||||
0x1D: ldstuba({{
|
||||
Rd.ub = Mem.ub;
|
||||
Mem.ub = 0xFF;
|
||||
}}); //LDSTUBA
|
||||
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
|
||||
0x1F: swapa({{
|
||||
UINT32 temp = Rd.uw;
|
||||
Rd.uw = Mem.uw;
|
||||
Mem.uw = temp;
|
||||
}}); //SWAPA
|
||||
0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
|
||||
0x21: decode X {
|
||||
0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
|
||||
0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
|
||||
}
|
||||
0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
|
||||
0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
|
||||
0x24: Trap::stf({{throw fp_disabled;}}); //STF
|
||||
0x25: decode X {
|
||||
0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
|
||||
0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
|
||||
}
|
||||
0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
|
||||
0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
0x2D: Noop::prefetch({{ }}); //PREFETCH
|
||||
|
||||
|
||||
0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
|
||||
|
||||
0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
|
||||
0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
|
||||
0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
|
||||
0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
|
||||
0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
0x3C: Cas::casa(
|
||||
{{UINT64 val = Mem.uw;
|
||||
if(Rs2.uw == val)
|
||||
Mem.uw = Rd.uw;
|
||||
Rd.uw = val;
|
||||
}}); //CASA
|
||||
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
||||
0x3E: Cas::casxa(
|
||||
{{UINT64 val = Mem.udw;
|
||||
if(Rs2 == val)
|
||||
Mem.udw = Rd;
|
||||
Rd = val;
|
||||
}}); //CASXA
|
||||
}
|
||||
}
|
||||
}
|
19
arch/sparc/isa_desc/formats.h
Normal file
19
arch/sparc/isa_desc/formats.h
Normal file
|
@ -0,0 +1,19 @@
|
|||
//Include the basic format
|
||||
//Templates from this format are used later
|
||||
##include "m5/arch/sparc/isa_desc/formats/basic.format"
|
||||
|
||||
//Include the integerOp and integerOpCc format
|
||||
##include "m5/arch/sparc/isa_desc/formats/integerop.format"
|
||||
|
||||
//Include the mem format
|
||||
##include "m5/arch/sparc/isa_desc/formats/mem.format"
|
||||
|
||||
//Include the trap format
|
||||
##include "m5/arch/sparc/isa_desc/formats/trap.format"
|
||||
|
||||
//Include the branch format
|
||||
##include "m5/arch/sparc/isa_desc/formats/branch.format"
|
||||
|
||||
//Include the noop format
|
||||
##include "m5/arch/sparc/isa_desc/formats/noop.format"
|
||||
|
65
arch/sparc/isa_desc/formats/basic.format
Normal file
65
arch/sparc/isa_desc/formats/basic.format
Normal file
|
@ -0,0 +1,65 @@
|
|||
|
||||
// Declarations for execute() methods.
|
||||
def template BasicExecDeclare {{
|
||||
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
||||
}};
|
||||
|
||||
// Basic instruction class declaration template.
|
||||
def template BasicDeclare {{
|
||||
/**
|
||||
* Static instruction class for "%(mnemonic)s".
|
||||
*/
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
/// Constructor.
|
||||
%(class_name)s(MachInst machInst);
|
||||
%(BasicExecDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
// Basic instruction class constructor template.
|
||||
def template BasicConstructor {{
|
||||
inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
||||
{
|
||||
%(constructor)s;
|
||||
}
|
||||
}};
|
||||
|
||||
// Basic instruction class execute method template.
|
||||
def template BasicExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = No_Fault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
|
||||
if(fault == No_Fault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Basic decode template.
|
||||
def template BasicDecode {{
|
||||
return new %(class_name)s(machInst);
|
||||
}};
|
||||
|
||||
// Basic decode template, passing mnemonic in as string arg to constructor.
|
||||
def template BasicDecodeWithMnemonic {{
|
||||
return new %(class_name)s("%(mnemonic)s", machInst);
|
||||
}};
|
||||
|
||||
// The most basic instruction format... used only for a few misc. insts
|
||||
def format BasicOperate(code, *flags) {{
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
66
arch/sparc/isa_desc/formats/branch.format
Normal file
66
arch/sparc/isa_desc/formats/branch.format
Normal file
|
@ -0,0 +1,66 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Branch instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class Branch : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template BranchExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Attempt to execute the instruction
|
||||
try
|
||||
{
|
||||
checkPriv;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
//If we have an exception for some reason,
|
||||
//deal with it
|
||||
catch(SparcException except)
|
||||
{
|
||||
//Deal with exception
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Branch(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = BranchExecute.subst(iop)
|
||||
}};
|
110
arch/sparc/isa_desc/formats/integerop.format
Normal file
110
arch/sparc/isa_desc/formats/integerop.format
Normal file
|
@ -0,0 +1,110 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Integer operate instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class IntegerOp : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template IntegerExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//These are set to constants when the execute method
|
||||
//is generated
|
||||
bool useCc = ;
|
||||
bool checkPriv = ;
|
||||
|
||||
//Attempt to execute the instruction
|
||||
try
|
||||
{
|
||||
checkPriv;
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
//If we have an exception for some reason,
|
||||
//deal with it
|
||||
catch(SparcException except)
|
||||
{
|
||||
//Deal with exception
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
if(useCc)
|
||||
{
|
||||
xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
|
||||
xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
|
||||
xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
|
||||
xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
|
||||
xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
|
||||
xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
|
||||
xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
|
||||
xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
|
||||
}
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntegerOp(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
checkPriv = (code.find('checkPriv') != -1)
|
||||
code.replace('checkPriv', '')
|
||||
if checkPriv:
|
||||
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
|
||||
else:
|
||||
code.replace('checkPriv;', '')
|
||||
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
|
||||
('xvValue', '0'), ('xcValue', '0')):
|
||||
code.replace(marker, value)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = IntegerExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
checkPriv = (code.find('checkPriv') != -1)
|
||||
code.replace('checkPriv', '')
|
||||
if checkPriv:
|
||||
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
|
||||
else:
|
||||
code.replace('checkPriv;', '')
|
||||
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
|
||||
('xvValue', xvValue), ('xcValue', xcValue)):
|
||||
code.replace(marker, value)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = IntegerExecute.subst(iop)
|
||||
}};
|
78
arch/sparc/isa_desc/formats/mem.format
Normal file
78
arch/sparc/isa_desc/formats/mem.format
Normal file
|
@ -0,0 +1,78 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Mem instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class Mem : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template MemExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Attempt to execute the instruction
|
||||
try
|
||||
{
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
ea_code
|
||||
%(code)s;
|
||||
}
|
||||
//If we have an exception for some reason,
|
||||
//deal with it
|
||||
catch(SparcException except)
|
||||
{
|
||||
//Deal with exception
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Mem(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = MemExecute.subst(iop)
|
||||
exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
|
||||
}};
|
||||
|
||||
def format Cas(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = MemExecute.subst(iop)
|
||||
exec_output.replace('ea_code', 'EA = R1;');
|
||||
}};
|
47
arch/sparc/isa_desc/formats/noop.format
Normal file
47
arch/sparc/isa_desc/formats/noop.format
Normal file
|
@ -0,0 +1,47 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Noop instruction
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class Noop : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template NoopExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Nothing to see here, move along
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Noop(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = NoopExecute.subst(iop)
|
||||
}};
|
53
arch/sparc/isa_desc/formats/trap.format
Normal file
53
arch/sparc/isa_desc/formats/trap.format
Normal file
|
@ -0,0 +1,53 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Trap instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class Trap : public SparcStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template TrapExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Call into the trap handler with the appropriate fault
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format Trap(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = CodeBlock(code)
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = TrapExecute.subst(iop)
|
||||
}};
|
40
arch/sparc/isa_desc/includes.h
Normal file
40
arch/sparc/isa_desc/includes.h
Normal file
|
@ -0,0 +1,40 @@
|
|||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Output include file directives.
|
||||
//
|
||||
|
||||
output header {{
|
||||
#include <sstream>
|
||||
#include <iostream>
|
||||
#include <iomanip>
|
||||
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "traps.hh"
|
||||
#include "mem/mem_req.hh" // some constructors use MemReq flags
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "cpu/exec_context.hh" // for Jump::branchTarget()
|
||||
|
||||
#include <math.h>
|
||||
#if defined(linux)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
#include <math.h>
|
||||
#if defined(linux)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
//#include "arch/alpha/pseudo_inst.hh"
|
||||
#endif
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/exetrace.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
}};
|
||||
|
61
arch/sparc/isa_desc/isa_desc
Normal file
61
arch/sparc/isa_desc/isa_desc
Normal file
|
@ -0,0 +1,61 @@
|
|||
// -*- mode:c++ -*-
|
||||
|
||||
//Copyright (c) 2003, 2004, 2005
|
||||
//The Regents of The University of Michigan
|
||||
//All Rights Reserved
|
||||
|
||||
//This code is part of the M5 simulator, developed by Nathan Binkert,
|
||||
//Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
|
||||
//from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,
|
||||
//and Andrew Schultz.
|
||||
|
||||
//Permission is granted to use, copy, create derivative works and
|
||||
//redistribute this software and such derivative works for any purpose,
|
||||
//so long as the copyright notice above, this grant of permission, and
|
||||
//the disclaimer below appear in all copies made; and so long as the
|
||||
//name of The University of Michigan is not used in any advertising or
|
||||
//publicity pertaining to the use or distribution of this software
|
||||
//without specific, written prior authorization.
|
||||
|
||||
//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
|
||||
//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
|
||||
//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
|
||||
//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
|
||||
//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
|
||||
//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
|
||||
//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
|
||||
//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
|
||||
//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
|
||||
//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// SPARC ISA description file.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Include the C++ include directives
|
||||
##include "m5/arch/sparc/isa_desc/includes.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Namespace statement. Everything below this line will be in the
|
||||
// SparcISAInst namespace.
|
||||
//
|
||||
|
||||
namespace SparcISA;
|
||||
|
||||
//Include the bitfield definitions
|
||||
##include "m5/arch/sparc/isa_desc/bitfields.h"
|
||||
|
||||
//Include the operand_types and operand definitions
|
||||
##include "m5/arch/sparc/isa_desc/operands.h"
|
||||
|
||||
//Include the base class for sparc instructions, and some support code
|
||||
##include "m5/arch/sparc/isa_desc/base.h"
|
||||
|
||||
//Include the definitions for the instruction formats
|
||||
##include "m5/arch/sparc/isa_desc/formats.h"
|
||||
|
||||
//Include the decoder definition
|
||||
##include "m5/arch/sparc/isa_desc/decoder.h"
|
33
arch/sparc/isa_desc/operands.h
Normal file
33
arch/sparc/isa_desc/operands.h
Normal file
|
@ -0,0 +1,33 @@
|
|||
def operand_types {{
|
||||
'sb' : ('signed int', 8),
|
||||
'ub' : ('unsigned int', 8),
|
||||
'shw' : ('signed int', 16),
|
||||
'uhw' : ('unsigned int', 16),
|
||||
'sw' : ('signed int', 32),
|
||||
'uw' : ('unsigned int', 32),
|
||||
'sdw' : ('signed int', 64),
|
||||
'udw' : ('unsigned int', 64),
|
||||
'sf' : ('float', 32),
|
||||
'df' : ('float', 64),
|
||||
'qf' : ('float', 128)
|
||||
}};
|
||||
|
||||
def operands {{
|
||||
# Int regs default to unsigned, but code should not count on this.
|
||||
# For clarity, descriptions that depend on unsigned behavior should
|
||||
# explicitly specify '.uq'.
|
||||
'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
|
||||
'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
|
||||
'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
|
||||
#'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
|
||||
#'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
|
||||
#'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
|
||||
'Mem': MemOperandTraits('udw', None,
|
||||
('IsMemRef', 'IsLoad', 'IsStore'), 4)
|
||||
#'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
|
||||
#'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
|
||||
#'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
|
||||
# The next two are hacks for non-full-system call-pal emulation
|
||||
#'R0': IntRegOperandTraits('uq', '0', None, 1),
|
||||
#'R16': IntRegOperandTraits('uq', '16', None, 1)
|
||||
}};
|
528
arch/sparc/isa_traits.hh
Normal file
528
arch/sparc/isa_traits.hh
Normal file
|
@ -0,0 +1,528 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
|
||||
#define __ARCH_SPARC_ISA_TRAITS_HH__
|
||||
|
||||
#include "arch/sparc/faults.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
class FastCPU;
|
||||
//class FullCPU;
|
||||
//class Checkpoint;
|
||||
|
||||
#define TARGET_SPARC
|
||||
|
||||
template <class ISA> class StaticInst;
|
||||
template <class ISA> class StaticInstPtr;
|
||||
|
||||
//namespace EV5
|
||||
//{
|
||||
// int DTB_ASN_ASN(uint64_t reg);
|
||||
// int ITB_ASN_ASN(uint64_t reg);
|
||||
//}
|
||||
|
||||
class SPARCISA
|
||||
{
|
||||
public:
|
||||
|
||||
typedef uint32_t MachInst;
|
||||
typedef uint64_t Addr;
|
||||
typedef uint8_t RegIndex;
|
||||
|
||||
enum
|
||||
{
|
||||
MemoryEnd = 0xffffffffffffffffULL,
|
||||
|
||||
NumFloatRegs = 32,
|
||||
NumMiscRegs = 32,
|
||||
|
||||
MaxRegsOfAnyType = 32,
|
||||
// Static instruction parameters
|
||||
MaxInstSrcRegs = 3,
|
||||
MaxInstDestRegs = 2,
|
||||
|
||||
// Maximum trap level
|
||||
MaxTL = 4
|
||||
|
||||
// semantically meaningful register indices
|
||||
ZeroReg = 0, // architecturally meaningful
|
||||
// the rest of these depend on the ABI
|
||||
}
|
||||
typedef uint64_t IntReg;
|
||||
|
||||
class IntRegFile
|
||||
{
|
||||
private:
|
||||
//For right now, let's pretend the register file is static
|
||||
IntReg regs[32];
|
||||
public:
|
||||
IntReg & operator [] (RegIndex index)
|
||||
{
|
||||
//Don't allow indexes outside of the 32 registers
|
||||
index &= 0x1F
|
||||
return regs[index];
|
||||
}
|
||||
};
|
||||
|
||||
void inline serialize(std::ostream & os)
|
||||
{
|
||||
SERIALIZE_ARRAY(regs, 32);
|
||||
}
|
||||
|
||||
void inline unserialize(Checkpoint &*cp, const std::string §ion)
|
||||
{
|
||||
UNSERIALIZE_ARRAY(regs, 32);
|
||||
}
|
||||
|
||||
class FloatRegFile
|
||||
{
|
||||
private:
|
||||
//By using the largest data type, we ensure everything
|
||||
//is aligned correctly in memory
|
||||
union
|
||||
{
|
||||
double double rawRegs[16];
|
||||
uint64_t regDump[32];
|
||||
};
|
||||
class QuadRegs
|
||||
{
|
||||
private:
|
||||
FloatRegFile * parent;
|
||||
public:
|
||||
QuadRegs(FloatRegFile * p) : parent(p) {;}
|
||||
double double & operator [] (RegIndex index)
|
||||
{
|
||||
//Quad floats are index by the single
|
||||
//precision register the start on,
|
||||
//and only 16 should be accessed
|
||||
index = (index >> 2) & 0xF;
|
||||
return parent->rawRegs[index];
|
||||
}
|
||||
};
|
||||
class DoubleRegs
|
||||
{
|
||||
private:
|
||||
FloatRegFile * parent;
|
||||
public:
|
||||
DoubleRegs(FloatRegFile * p) : parent(p) {;}
|
||||
double & operator [] (RegIndex index)
|
||||
{
|
||||
//Double floats are index by the single
|
||||
//precision register the start on,
|
||||
//and only 32 should be accessed
|
||||
index = (index >> 1) & 0x1F
|
||||
return ((double [])parent->rawRegs)[index];
|
||||
}
|
||||
}
|
||||
class SingleRegs
|
||||
{
|
||||
private:
|
||||
FloatRegFile * parent;
|
||||
public:
|
||||
SingleRegs(FloatRegFile * p) : parent(p) {;}
|
||||
double & operator [] (RegFile index)
|
||||
{
|
||||
//Only 32 single floats should be accessed
|
||||
index &= 0x1F
|
||||
return ((float [])parent->rawRegs)[index];
|
||||
}
|
||||
}
|
||||
public:
|
||||
void inline serialize(std::ostream & os)
|
||||
{
|
||||
SERIALIZE_ARRAY(regDump, 32);
|
||||
}
|
||||
|
||||
void inline unserialize(Checkpoint &* cp, std::string & section)
|
||||
{
|
||||
UNSERIALIZE_ARRAY(regDump, 32);
|
||||
}
|
||||
|
||||
QuadRegs quadRegs;
|
||||
DoubleRegs doubleRegs;
|
||||
SingleRegs singleRegs;
|
||||
FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
|
||||
{;}
|
||||
};
|
||||
|
||||
// control register file contents
|
||||
typedef uint64_t MiscReg;
|
||||
// The control registers, broken out into fields
|
||||
class MiscRegFile
|
||||
{
|
||||
public:
|
||||
union
|
||||
{
|
||||
uint16_t pstate; // Process State Register
|
||||
struct
|
||||
{
|
||||
uint16_t ag:1; // Alternate Globals
|
||||
uint16_t ie:1; // Interrupt enable
|
||||
uint16_t priv:1; // Privelege mode
|
||||
uint16_t am:1; // Address mask
|
||||
uint16_t pef:1; // PSTATE enable floating-point
|
||||
uint16_t red:1; // RED (reset, error, debug) state
|
||||
uint16_t mm:2; // Memory Model
|
||||
uint16_t tle:1; // Trap little-endian
|
||||
uint16_t cle:1; // Current little-endian
|
||||
} pstateFields;
|
||||
}
|
||||
uint64_t tba; // Trap Base Address
|
||||
union
|
||||
{
|
||||
uint64_t y; // Y (used in obsolete multiplication)
|
||||
struct
|
||||
{
|
||||
uint64_t value:32; // The actual value stored in y
|
||||
const uint64_t :32; // reserved bits
|
||||
} yFields;
|
||||
}
|
||||
uint8_t pil; // Process Interrupt Register
|
||||
uint8_t cwp; // Current Window Pointer
|
||||
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level)
|
||||
union
|
||||
{
|
||||
uint8_t ccr; // Condition Code Register
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
uint8_t icc:4; // 32-bit condition codes
|
||||
struct
|
||||
{
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} iccFields:4;
|
||||
} :4;
|
||||
union
|
||||
{
|
||||
uint8_t xcc:4; // 64-bit condition codes
|
||||
struct
|
||||
{
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} xccFields:4;
|
||||
} :4;
|
||||
} ccrFields;
|
||||
}
|
||||
uint8_t asi; // Address Space Identifier
|
||||
uint8_t tl; // Trap Level
|
||||
uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level)
|
||||
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level)
|
||||
union
|
||||
{
|
||||
uint64_t tstate[MaxTL]; // Trap State
|
||||
struct
|
||||
{
|
||||
//Values are from previous trap level
|
||||
uint64_t cwp:5; // Current Window Pointer
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t pstate:10; // Process State
|
||||
const uint64_t :6; // Reserved bits
|
||||
uint64_t asi:8; // Address Space Identifier
|
||||
uint64_t ccr:8; // Condition Code Register
|
||||
} tstateFields[MaxTL];
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t tick; // Hardware clock-tick counter
|
||||
struct
|
||||
{
|
||||
uint64_t counter:63; // Clock-tick count
|
||||
uint64_t npt:1; // Non-priveleged trap
|
||||
} tickFields;
|
||||
}
|
||||
uint8_t cansave; // Savable windows
|
||||
uint8_t canrestore; // Restorable windows
|
||||
uint8_t otherwin; // Other windows
|
||||
uint8_t cleanwin; // Clean windows
|
||||
union
|
||||
{
|
||||
uint8_t wstate; // Window State
|
||||
struct
|
||||
{
|
||||
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
|
||||
// register window trap
|
||||
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
||||
// register window trap
|
||||
} wstateFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t ver; // Version
|
||||
struct
|
||||
{
|
||||
uint64_t maxwin:5; // Max CWP value
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t maxtl:8; // Maximum trap level
|
||||
const uint64_t :8; // Reserved bits
|
||||
uint64_t mask:8; // Processor mask set revision number
|
||||
uint64_t impl:16; // Implementation identification number
|
||||
uint64_t manuf:16; // Manufacturer code
|
||||
} verFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint64_t fsr; // Floating-Point State Register
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
uint64_t cexc:5; // Current excpetion
|
||||
struct
|
||||
{
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} cexecFields:5;
|
||||
} :5;
|
||||
union
|
||||
{
|
||||
uint64_t aexc:5; // Accrued exception
|
||||
struct
|
||||
{
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} aexecFields:5;
|
||||
} :5;
|
||||
uint64_t fcc0:2; // Floating-Point condtion codes
|
||||
const uint64_t :1; // Reserved bits
|
||||
uint64_t qne:1; // Deferred trap queue not empty
|
||||
// with no queue, it should read 0
|
||||
uint64_t ftt:3; // Floating-Point trap type
|
||||
uint64_t ver:3; // Version (of the FPU)
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t ns:1; // Nonstandard floating point
|
||||
union
|
||||
{
|
||||
uint64_t tem:5; // Trap Enable Mask
|
||||
struct
|
||||
{
|
||||
uint64_t nxm:1; // Inexact
|
||||
uint64_t dzm:1; // Divide by zero
|
||||
uint64_t ufm:1; // Underflow
|
||||
uint64_t ofm:1; // Overflow
|
||||
uint64_t nvm:1; // Invalid operand
|
||||
} temFields:5;
|
||||
} :5;
|
||||
const uint64_t :2; // Reserved bits
|
||||
uint64_t rd:2; // Rounding direction
|
||||
uint64_t fcc1:2; // Floating-Point condition codes
|
||||
uint64_t fcc2:2; // Floating-Point condition codes
|
||||
uint64_t fcc3:2; // Floating-Point condition codes
|
||||
const uint64_t :26; // Reserved bits
|
||||
} fsrFields;
|
||||
}
|
||||
union
|
||||
{
|
||||
uint8_t fprs; // Floating-Point Register State
|
||||
struct
|
||||
{
|
||||
dl:1; // Dirty lower
|
||||
du:1; // Dirty upper
|
||||
fef:1; // FPRS enable floating-Point
|
||||
} fprsFields;
|
||||
};
|
||||
|
||||
void serialize(std::ostream & os)
|
||||
{
|
||||
SERIALIZE_SCALAR(pstate);
|
||||
SERIAlIZE_SCALAR(tba);
|
||||
SERIALIZE_SCALAR(y);
|
||||
SERIALIZE_SCALAR(pil);
|
||||
SERIALIZE_SCALAR(cwp);
|
||||
SERIALIZE_ARRAY(tt, MaxTL);
|
||||
SERIALIZE_SCALAR(ccr);
|
||||
SERIALIZE_SCALAR(asi);
|
||||
SERIALIZE_SCALAR(tl);
|
||||
SERIALIZE_SCALAR(tpc);
|
||||
SERIALIZE_SCALAR(tnpc);
|
||||
SERIALIZE_ARRAY(tstate, MaxTL);
|
||||
SERIALIZE_SCALAR(tick);
|
||||
SERIALIZE_SCALAR(cansave);
|
||||
SERIALIZE_SCALAR(canrestore);
|
||||
SERIALIZE_SCALAR(otherwin);
|
||||
SERIALIZE_SCALAR(cleanwin);
|
||||
SERIALIZE_SCALAR(wstate);
|
||||
SERIALIZE_SCALAR(ver);
|
||||
SERIALIZE_SCALAR(fsr);
|
||||
SERIALIZE_SCALAR(fprs);
|
||||
}
|
||||
|
||||
void unserialize(Checkpoint &* cp, std::string & section)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(pstate);
|
||||
UNSERIAlIZE_SCALAR(tba);
|
||||
UNSERIALIZE_SCALAR(y);
|
||||
UNSERIALIZE_SCALAR(pil);
|
||||
UNSERIALIZE_SCALAR(cwp);
|
||||
UNSERIALIZE_ARRAY(tt, MaxTL);
|
||||
UNSERIALIZE_SCALAR(ccr);
|
||||
UNSERIALIZE_SCALAR(asi);
|
||||
UNSERIALIZE_SCALAR(tl);
|
||||
UNSERIALIZE_SCALAR(tpc);
|
||||
UNSERIALIZE_SCALAR(tnpc);
|
||||
UNSERIALIZE_ARRAY(tstate, MaxTL);
|
||||
UNSERIALIZE_SCALAR(tick);
|
||||
UNSERIALIZE_SCALAR(cansave);
|
||||
UNSERIALIZE_SCALAR(canrestore);
|
||||
UNSERIALIZE_SCALAR(otherwin);
|
||||
UNSERIALIZE_SCALAR(cleanwin);
|
||||
UNSERIALIZE_SCALAR(wstate);
|
||||
UNSERIALIZE_SCALAR(ver);
|
||||
UNSERIALIZE_SCALAR(fsr);
|
||||
UNSERIALIZE_SCALAR(fprs);
|
||||
}
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
IntReg intreg;
|
||||
FloatReg fpreg;
|
||||
MiscReg ctrlreg;
|
||||
} AnyReg;
|
||||
|
||||
struct RegFile
|
||||
{
|
||||
IntRegFile intRegFile; // (signed) integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
|
||||
Addr pc; // Program Counter
|
||||
Addr npc; // Next Program Counter
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
|
||||
|
||||
// return a no-op instruction... used for instruction fetch faults
|
||||
static const MachInst NoopMachInst;
|
||||
|
||||
// Instruction address compression hooks
|
||||
static inline Addr realPCToFetchPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline Addr fetchPCToRealPC(const Addr &addr)
|
||||
{
|
||||
return addr;
|
||||
}
|
||||
|
||||
// the size of "fetched" instructions (not necessarily the size
|
||||
// of real instructions for PISA)
|
||||
static inline size_t fetchInstSize()
|
||||
{
|
||||
return sizeof(MachInst);
|
||||
}
|
||||
|
||||
/**
|
||||
* Function to insure ISA semantics about 0 registers.
|
||||
* @param xc The execution context.
|
||||
*/
|
||||
template <class XC>
|
||||
static void zeroRegisters(XC *xc);
|
||||
};
|
||||
|
||||
|
||||
typedef SPARCISA TheISA;
|
||||
|
||||
typedef TheISA::MachInst MachInst;
|
||||
typedef TheISA::Addr Addr;
|
||||
typedef TheISA::RegIndex RegIndex;
|
||||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::IntRegFile IntRegFile;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegFile FloatRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::AnyReg AnyReg;
|
||||
typedef TheISA::RegFile RegFile;
|
||||
|
||||
const int VMPageSize = TheISA::VMPageSize;
|
||||
const int LogVMPageSize = TheISA::LogVMPageSize;
|
||||
const int ZeroReg = TheISA::ZeroReg;
|
||||
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
|
||||
const int MaxAddr = (Addr)-1;
|
||||
|
||||
#ifndef FULL_SYSTEM
|
||||
class SyscallReturn {
|
||||
public:
|
||||
template <class T>
|
||||
SyscallReturn(T v, bool s)
|
||||
{
|
||||
retval = (uint64_t)v;
|
||||
success = s;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
SyscallReturn(T v)
|
||||
{
|
||||
success = (v >= 0);
|
||||
retval = (uint64_t)v;
|
||||
}
|
||||
|
||||
~SyscallReturn() {}
|
||||
|
||||
SyscallReturn& operator=(const SyscallReturn& s) {
|
||||
retval = s.retval;
|
||||
success = s.success;
|
||||
return *this;
|
||||
}
|
||||
|
||||
bool successful() { return success; }
|
||||
uint64_t value() { return retval; }
|
||||
|
||||
|
||||
private:
|
||||
uint64_t retval;
|
||||
bool success;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
|
||||
#include "arch/alpha/ev5.hh"
|
||||
#endif
|
||||
|
||||
#endif // __ARCH_SPARC_ISA_TRAITS_HH__
|
Loading…
Reference in a new issue