cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.
This commit is contained in:
parent
9f63548478
commit
8b4e8690b7
9
src/mem/cache/cache_impl.hh
vendored
9
src/mem/cache/cache_impl.hh
vendored
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@ -266,7 +266,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
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return false;
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}
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blk = tags->accessBlock(pkt->getAddr(), lat);
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int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
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blk = tags->accessBlock(pkt->getAddr(), lat, id);
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DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
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pkt->req->isInstFetch() ? " (ifetch)" : "",
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@ -299,7 +300,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
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incMissCount(pkt);
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return false;
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}
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tags->insertBlock(pkt->getAddr(), blk);
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int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
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tags->insertBlock(pkt->getAddr(), blk, id);
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blk->status = BlkValid | BlkReadable;
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}
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std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
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@ -976,7 +978,8 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
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tempBlock->tag = tags->extractTag(addr);
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DPRINTF(Cache, "using temp block for %x\n", addr);
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} else {
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tags->insertBlock(addr, blk);
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int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
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tags->insertBlock(pkt->getAddr(), blk, id);
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}
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} else {
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// existing block... probably an upgrade
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4
src/mem/cache/tags/fa_lru.cc
vendored
4
src/mem/cache/tags/fa_lru.cc
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@ -154,7 +154,7 @@ FALRU::invalidateBlk(FALRU::BlkType *blk)
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}
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FALRUBlk*
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FALRU::accessBlock(Addr addr, int &lat, int *inCache)
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FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
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{
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accesses++;
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int tmp_in_cache = 0;
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@ -228,7 +228,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks)
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}
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void
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FALRU::insertBlock(Addr addr, FALRU::BlkType *blk)
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FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src)
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{
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}
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4
src/mem/cache/tags/fa_lru.hh
vendored
4
src/mem/cache/tags/fa_lru.hh
vendored
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@ -182,7 +182,7 @@ public:
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* @param inCache The FALRUBlk::inCache flags.
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* @return Pointer to the cache block.
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*/
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FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0);
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FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
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/**
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* Find the block in the cache, do not update the replacement data.
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@ -200,7 +200,7 @@ public:
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*/
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FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
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void insertBlock(Addr addr, BlkType *blk);
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void insertBlock(Addr addr, BlkType *blk, int context_src);
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/**
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* Return the hit latency of this cache.
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4
src/mem/cache/tags/iic.cc
vendored
4
src/mem/cache/tags/iic.cc
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@ -219,7 +219,7 @@ IIC::regStats(const string &name)
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IICTag*
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IIC::accessBlock(Addr addr, int &lat)
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IIC::accessBlock(Addr addr, int &lat, int context_src)
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{
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Addr tag = extractTag(addr);
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unsigned set = hash(addr);
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@ -338,7 +338,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks)
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}
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void
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IIC::insertBlock(Addr addr, BlkType* blk)
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IIC::insertBlock(Addr addr, BlkType* blk, int context_src)
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{
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}
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4
src/mem/cache/tags/iic.hh
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4
src/mem/cache/tags/iic.hh
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@ -422,7 +422,7 @@ class IIC : public BaseTags
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* @param lat The access latency.
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* @return A pointer to the block found, if any.
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*/
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IICTag* accessBlock(Addr addr, int &lat);
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IICTag* accessBlock(Addr addr, int &lat, int context_src);
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/**
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* Find the block, do not update the replacement data.
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@ -440,7 +440,7 @@ class IIC : public BaseTags
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*/
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IICTag* findVictim(Addr addr, PacketList &writebacks);
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void insertBlock(Addr addr, BlkType *blk);
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void insertBlock(Addr addr, BlkType *blk, int context_src);
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/**
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* Called at end of simulation to complete average block reference stats.
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4
src/mem/cache/tags/lru.cc
vendored
4
src/mem/cache/tags/lru.cc
vendored
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@ -150,7 +150,7 @@ LRU::~LRU()
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}
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LRUBlk*
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LRU::accessBlock(Addr addr, int &lat)
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LRU::accessBlock(Addr addr, int &lat, int context_src)
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{
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Addr tag = extractTag(addr);
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unsigned set = extractSet(addr);
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@ -200,7 +200,7 @@ LRU::findVictim(Addr addr, PacketList &writebacks)
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}
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void
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LRU::insertBlock(Addr addr, LRU::BlkType *blk)
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LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src)
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{
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if (!blk->isTouched) {
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tagsInUse++;
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4
src/mem/cache/tags/lru.hh
vendored
4
src/mem/cache/tags/lru.hh
vendored
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@ -172,7 +172,7 @@ public:
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* @param lat The access latency.
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* @return Pointer to the cache block if found.
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*/
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LRUBlk* accessBlock(Addr addr, int &lat);
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LRUBlk* accessBlock(Addr addr, int &lat, int context_src);
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/**
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* Finds the given address in the cache, do not update replacement data.
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@ -197,7 +197,7 @@ public:
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* @param addr The address to update.
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* @param blk The block to update.
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*/
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void insertBlock(Addr addr, BlkType *blk);
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void insertBlock(Addr addr, BlkType *blk, int context_src);
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/**
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* Generate the tag from the given address.
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