TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
This commit is contained in:
parent
7bde0285e5
commit
8b4796a367
16 changed files with 140 additions and 14 deletions
|
@ -58,7 +58,7 @@ bool uncacheBit40 = false;
|
|||
#define MODE2MASK(X) (1 << (X))
|
||||
|
||||
TLB::TLB(const Params *p)
|
||||
: SimObject(p), size(p->size), nlu(0)
|
||||
: BaseTLB(p), size(p->size), nlu(0)
|
||||
{
|
||||
table = new TlbEntry[size];
|
||||
memset(table, 0, sizeof(TlbEntry[size]));
|
||||
|
|
|
@ -44,7 +44,7 @@
|
|||
#include "params/AlphaDTB.hh"
|
||||
#include "params/AlphaITB.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/tlb.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
||||
|
@ -52,7 +52,7 @@ namespace AlphaISA
|
|||
{
|
||||
class TlbEntry;
|
||||
|
||||
class TLB : public SimObject
|
||||
class TLB : public BaseTLB
|
||||
{
|
||||
protected:
|
||||
typedef std::multimap<Addr, int> PageTable;
|
||||
|
@ -79,6 +79,12 @@ namespace AlphaISA
|
|||
void flushProcesses();
|
||||
void flushAddr(Addr addr, uint8_t asn);
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
assert(asn < (1 << 8));
|
||||
flushAddr(vaddr, asn);
|
||||
}
|
||||
|
||||
// static helper functions... really EV5 VM traits
|
||||
static bool validVirtualAddress(Addr vaddr) {
|
||||
// unimplemented bits must be all 0 or all 1
|
||||
|
|
|
@ -62,7 +62,7 @@ using namespace MipsISA;
|
|||
#define MODE2MASK(X) (1 << (X))
|
||||
|
||||
TLB::TLB(const Params *p)
|
||||
: SimObject(p), size(p->size), nlu(0)
|
||||
: BaseTLB(p), size(p->size), nlu(0)
|
||||
{
|
||||
table = new MipsISA::PTE[size];
|
||||
memset(table, 0, sizeof(MipsISA::PTE[size]));
|
||||
|
|
|
@ -80,7 +80,7 @@ struct TlbEntry
|
|||
|
||||
};
|
||||
|
||||
class TLB : public SimObject
|
||||
class TLB : public BaseTLB
|
||||
{
|
||||
protected:
|
||||
typedef std::multimap<Addr, int> PageTable;
|
||||
|
@ -120,6 +120,10 @@ class TLB : public SimObject
|
|||
void insert(Addr vaddr, MipsISA::PTE &pte);
|
||||
void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
|
||||
void flushAll();
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
panic("demapPage unimplemented.\n");
|
||||
}
|
||||
|
||||
// static helper functions... really
|
||||
static bool validVirtualAddress(Addr vaddr);
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
namespace SparcISA {
|
||||
|
||||
TLB::TLB(const Params *p)
|
||||
: SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
|
||||
: BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
|
||||
cacheValid(false)
|
||||
{
|
||||
// To make this work you'll have to change the hypervisor and OS
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
#include "params/SparcDTB.hh"
|
||||
#include "params/SparcITB.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/tlb.hh"
|
||||
|
||||
class ThreadContext;
|
||||
class Packet;
|
||||
|
@ -47,7 +47,7 @@ class Packet;
|
|||
namespace SparcISA
|
||||
{
|
||||
|
||||
class TLB : public SimObject
|
||||
class TLB : public BaseTLB
|
||||
{
|
||||
#if !FULL_SYSTEM
|
||||
//These faults need to be able to populate the tlb in SE mode.
|
||||
|
@ -152,6 +152,11 @@ class TLB : public SimObject
|
|||
typedef SparcTLBParams Params;
|
||||
TLB(const Params *p);
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
panic("demapPage(Addr) is not implemented.\n");
|
||||
}
|
||||
|
||||
void dumpAll();
|
||||
|
||||
// Checkpointing
|
||||
|
|
|
@ -76,7 +76,7 @@
|
|||
|
||||
namespace X86ISA {
|
||||
|
||||
TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size)
|
||||
TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
|
||||
{
|
||||
tlb = new TlbEntry[size];
|
||||
std::memset(tlb, 0, sizeof(TlbEntry) * size);
|
||||
|
@ -169,7 +169,7 @@ TLB::invalidateNonGlobal()
|
|||
}
|
||||
|
||||
void
|
||||
TLB::demapPage(Addr va)
|
||||
TLB::demapPage(Addr va, uint64_t asn)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
|
@ -70,6 +70,7 @@
|
|||
#include "params/X86DTB.hh"
|
||||
#include "params/X86ITB.hh"
|
||||
#include "sim/faults.hh"
|
||||
#include "sim/tlb.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class ThreadContext;
|
||||
|
@ -83,7 +84,7 @@ namespace X86ISA
|
|||
|
||||
class TLB;
|
||||
|
||||
class TLB : public SimObject
|
||||
class TLB : public BaseTLB
|
||||
{
|
||||
protected:
|
||||
friend class FakeITLBFault;
|
||||
|
@ -120,7 +121,7 @@ namespace X86ISA
|
|||
|
||||
void invalidateNonGlobal();
|
||||
|
||||
void demapPage(Addr va);
|
||||
void demapPage(Addr va, uint64_t asn);
|
||||
|
||||
protected:
|
||||
int size;
|
||||
|
|
|
@ -92,6 +92,19 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
|||
/** InstRecord that tracks this instructions. */
|
||||
Trace::InstRecord *traceData;
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
cpu->demapPage(vaddr, asn);
|
||||
}
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
cpu->demapPage(vaddr, asn);
|
||||
}
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
cpu->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
/**
|
||||
* Does a read to a given address.
|
||||
* @param addr The address to read.
|
||||
|
|
|
@ -324,6 +324,22 @@ class CheckerCPU : public BaseCPU
|
|||
void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
|
||||
void recordNextPCChange(uint64_t val) { changedNextPC = true; }
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->itb->demapPage(vaddr, asn);
|
||||
this->dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->itb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
bool translateInstReq(Request *req);
|
||||
void translateDataWriteReq(Request *req);
|
||||
void translateDataReadReq(Request *req);
|
||||
|
|
|
@ -263,6 +263,22 @@ class FullO3CPU : public BaseO3CPU
|
|||
/** Registers statistics. */
|
||||
void fullCPURegStats();
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->itb->demapPage(vaddr, asn);
|
||||
this->dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->itb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
this->dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
/** Translates instruction requestion. */
|
||||
Fault translateInstReq(RequestPtr &req, Thread *thread)
|
||||
{
|
||||
|
|
|
@ -423,6 +423,22 @@ class OzoneCPU : public BaseCPU
|
|||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
itb->demap(vaddr, asn);
|
||||
dtb->demap(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
itb->demap(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
dtb->demap(vaddr, asn);
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
/** Translates instruction requestion. */
|
||||
Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
|
||||
|
|
|
@ -367,6 +367,21 @@ class BaseSimpleCPU : public BaseCPU
|
|||
return thread->setMiscReg(reg_idx, val);
|
||||
}
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
thread->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
thread->demapInstPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
thread->demapDataPage(vaddr, asn);
|
||||
}
|
||||
|
||||
unsigned readStCondFailures() {
|
||||
return thread->readStCondFailures();
|
||||
}
|
||||
|
|
|
@ -163,6 +163,22 @@ class SimpleThread : public ThreadState
|
|||
return dtb->translate(req, tc, true);
|
||||
}
|
||||
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
itb->demapPage(vaddr, asn);
|
||||
dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapInstPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
itb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
void demapDataPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
dtb->demapPage(vaddr, asn);
|
||||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
int getInstAsid() { return regs.instAsid(); }
|
||||
int getDataAsid() { return regs.dataAsid(); }
|
||||
|
|
|
@ -48,3 +48,9 @@ GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool)
|
|||
return NoFault;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
GenericTLB::demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
warn("Demapping pages in the generic TLB is unnecessary.\n");
|
||||
}
|
||||
|
|
|
@ -39,13 +39,25 @@
|
|||
class ThreadContext;
|
||||
class Packet;
|
||||
|
||||
class GenericTLB : public SimObject
|
||||
class BaseTLB : public SimObject
|
||||
{
|
||||
protected:
|
||||
GenericTLB(const Params *p) : SimObject(p)
|
||||
BaseTLB(const Params *p) : SimObject(p)
|
||||
{}
|
||||
|
||||
public:
|
||||
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
|
||||
};
|
||||
|
||||
class GenericTLB : public BaseTLB
|
||||
{
|
||||
protected:
|
||||
GenericTLB(const Params *p) : BaseTLB(p)
|
||||
{}
|
||||
|
||||
public:
|
||||
void demapPage(Addr vaddr, uint64_t asn);
|
||||
|
||||
Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue