X86: Update stats for the updated auxilliary vectors.
This commit is contained in:
parent
2ee7a89209
commit
8b0c83008e
36 changed files with 756 additions and 752 deletions
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@ -57,7 +57,7 @@ egid=100
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env=
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env=
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errout=cerr
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errout=cerr
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euid=100
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euid=100
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executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
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executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
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gid=100
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gid=100
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input=cin
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input=cin
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max_stack_size=67108864
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max_stack_size=67108864
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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All Rights Reserved
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M5 compiled Feb 25 2010 03:41:05
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M5 compiled May 2 2010 23:23:01
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M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
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M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
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M5 started Feb 25 2010 03:41:09
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M5 started May 2 2010 23:23:02
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M5 executing on SC2B0619
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M5 executing on burrito
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Entering event queue @ 0. Starting simulation...
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@ -44,4 +44,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Tested 1MB buffer: OK!
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Exiting @ tick 962929075000 because target called exit()
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Exiting @ tick 962929106000 because target called exit()
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@ -1,18 +1,18 @@
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---------- Begin Simulation Statistics ----------
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1572419 # Simulator instruction rate (inst/s)
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host_inst_rate 3183370 # Simulator instruction rate (inst/s)
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host_mem_usage 188984 # Number of bytes of host memory used
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host_mem_usage 217548 # Number of bytes of host memory used
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host_seconds 1029.86 # Real time elapsed on the host
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host_seconds 508.70 # Real time elapsed on the host
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host_tick_rate 935012313 # Simulator tick rate (ticks/s)
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host_tick_rate 1892936287 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1619366736 # Number of instructions simulated
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sim_insts 1619366787 # Number of instructions simulated
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sim_seconds 0.962929 # Number of seconds simulated
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sim_seconds 0.962929 # Number of seconds simulated
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sim_ticks 962929075000 # Number of ticks simulated
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sim_ticks 962929106000 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1925858151 # number of cpu cycles simulated
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system.cpu.numCycles 1925858213 # number of cpu cycles simulated
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system.cpu.num_insts 1619366736 # Number of instructions executed
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system.cpu.num_insts 1619366787 # Number of instructions executed
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system.cpu.num_refs 607228174 # Number of memory references
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system.cpu.num_refs 607228182 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
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system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
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---------- End Simulation Statistics ----------
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---------- End Simulation Statistics ----------
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@ -157,7 +157,7 @@ egid=100
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env=
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env=
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errout=cerr
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errout=cerr
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euid=100
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euid=100
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executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
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executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
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gid=100
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gid=100
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input=cin
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input=cin
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max_stack_size=67108864
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max_stack_size=67108864
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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All Rights Reserved
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M5 compiled Feb 25 2010 03:41:05
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M5 compiled May 2 2010 23:23:01
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M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
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M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
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M5 started Feb 25 2010 03:47:37
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M5 started May 2 2010 23:23:02
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M5 executing on SC2B0619
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M5 executing on burrito
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Entering event queue @ 0. Starting simulation...
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@ -44,4 +44,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Tested 1MB buffer: OK!
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Exiting @ tick 1814726932000 because target called exit()
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Exiting @ tick 1814725999000 because target called exit()
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@ -1,82 +1,82 @@
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---------- Begin Simulation Statistics ----------
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---------- Begin Simulation Statistics ----------
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host_inst_rate 992380 # Simulator instruction rate (inst/s)
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host_inst_rate 1830893 # Simulator instruction rate (inst/s)
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host_mem_usage 196544 # Number of bytes of host memory used
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host_mem_usage 225176 # Number of bytes of host memory used
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host_seconds 1631.80 # Real time elapsed on the host
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host_seconds 884.47 # Real time elapsed on the host
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host_tick_rate 1112100106 # Simulator tick rate (ticks/s)
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host_tick_rate 2051770366 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1619366736 # Number of instructions simulated
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sim_insts 1619366787 # Number of instructions simulated
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sim_seconds 1.814727 # Number of seconds simulated
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sim_seconds 1.814726 # Number of seconds simulated
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sim_ticks 1814726932000 # Number of ticks simulated
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sim_ticks 1814725999000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 20884.820230 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency 20886.624165 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17884.820230 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17886.624165 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 418844783 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4121306000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency 4121474000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 197335 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3529301000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency 3529496000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 197335 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 187876631 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits 187876653 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 17327800000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 17326624000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 309425 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses 309404 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 16399525000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 16398412000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 309425 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 309404 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1372.614288 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 42325.964954 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency 42326.481558 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 606721414 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits 606721452 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 21449106000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency 21448098000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000835 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 506760 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses 506730 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 19928826000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 19927908000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000835 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 506760 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses 506730 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
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system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.901154 # Average occupied blocks per context
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system.cpu.dcache.occ_blocks::0 4094.901606 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 42326.481558 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 606721414 # number of overall hits
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system.cpu.dcache.overall_hits 606721452 # number of overall hits
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system.cpu.dcache.overall_miss_latency 21449106000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency 21448098000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000835 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 506760 # number of overall misses
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system.cpu.dcache.overall_misses 506730 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 19928826000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 19927908000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000835 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 506760 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses 506730 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 437970 # number of replacements
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system.cpu.dcache.replacements 437952 # number of replacements
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system.cpu.dcache.sampled_refs 442066 # Sample count of references to valid blocks.
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system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.901154 # Cycle average of tags in use
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system.cpu.dcache.tagsinuse 4094.901606 # Cycle average of tags in use
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system.cpu.dcache.total_refs 606786108 # Total number of references to valid blocks.
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system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 779430000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.warmup_cycle 779585000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 306212 # number of writebacks
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system.cpu.dcache.writebacks 306191 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1186516703 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1186515981 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
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@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms
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system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1643373.934903 # Average number of references to valid blocks.
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system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 1186516703 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 1186515981 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
|
||||||
|
@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 660.164909 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 660.164839 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 1186515981 # number of overall hits
|
system.cpu.icache.overall_hits 1186516018 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 722 # number of overall misses
|
system.cpu.icache.overall_misses 722 # number of overall misses
|
||||||
|
@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
||||||
system.cpu.icache.replacements 4 # number of replacements
|
system.cpu.icache.replacements 4 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 660.164909 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 660.164839 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 1186515981 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.l2cache.ReadExReq_accesses 244731 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 12726012000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 12725544000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 244731 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 244722 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9789240000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9788880000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 244731 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 244722 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 198057 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 164987 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 164971 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 1719640000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 1720004000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.166972 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.167015 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 33070 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 33077 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1322800000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1323080000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166972 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.167015 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 33070 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 33077 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 64694 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 64682 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 3364088000 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 3363464000 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 64694 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 64682 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587760000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587280000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 64694 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 64682 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.Writeback_accesses 306212 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 306191 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_hits 306212 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 306191 # number of Writeback hits
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 3.429569 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 3.428492 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 442788 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 164987 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 164971 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 14445652000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 14445548000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.627391 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.627412 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 277801 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 277799 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 11112040000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 11111960000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.627391 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.627412 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 277801 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 277799 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.052737 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.052754 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_%::1 0.452189 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::1 0.452175 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 1728.087970 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 1728.633036 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 14817.313734 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 14816.859075 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 164987 # number of overall hits
|
system.cpu.l2cache.overall_hits 164971 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 14445652000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 14445548000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.627391 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.627412 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 277801 # number of overall misses
|
system.cpu.l2cache.overall_misses 277799 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 11112040000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 11111960000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.627391 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.627412 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 277801 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 277799 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 81543 # number of replacements
|
system.cpu.l2cache.replacements 81557 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 97060 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 97073 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 16545.401704 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 16545.492111 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 332874 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 332814 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 61555 # number of writebacks
|
system.cpu.l2cache.writebacks 61569 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 3629453864 # number of cpu cycles simulated
|
system.cpu.numCycles 3629451998 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 1619366736 # Number of instructions executed
|
system.cpu.num_insts 1619366787 # Number of instructions executed
|
||||||
system.cpu.num_refs 607228174 # Number of memory references
|
system.cpu.num_refs 607228182 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -57,9 +57,9 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
|
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||||
gid=100
|
gid=100
|
||||||
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
|
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:50:08
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -28,4 +28,4 @@ simplex iterations : 2663
|
||||||
flow value : 3080014995
|
flow value : 3080014995
|
||||||
checksum : 68389
|
checksum : 68389
|
||||||
optimal
|
optimal
|
||||||
Exiting @ tick 164701786000 because target called exit()
|
Exiting @ tick 164701817000 because target called exit()
|
||||||
|
|
|
@ -1,18 +1,18 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 1130966 # Simulator instruction rate (inst/s)
|
host_inst_rate 3001240 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 323116 # Number of bytes of host memory used
|
host_mem_usage 352084 # Number of bytes of host memory used
|
||||||
host_seconds 238.47 # Real time elapsed on the host
|
host_seconds 89.86 # Real time elapsed on the host
|
||||||
host_tick_rate 690673696 # Simulator tick rate (ticks/s)
|
host_tick_rate 1832836403 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 269695959 # Number of instructions simulated
|
sim_insts 269696010 # Number of instructions simulated
|
||||||
sim_seconds 0.164702 # Number of seconds simulated
|
sim_seconds 0.164702 # Number of seconds simulated
|
||||||
sim_ticks 164701786000 # Number of ticks simulated
|
sim_ticks 164701817000 # Number of ticks simulated
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 329403573 # number of cpu cycles simulated
|
system.cpu.numCycles 329403635 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 269695959 # Number of instructions executed
|
system.cpu.num_insts 269696010 # Number of instructions executed
|
||||||
system.cpu.num_refs 122219131 # Number of memory references
|
system.cpu.num_refs 122219139 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -157,9 +157,9 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/mcf
|
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||||
gid=100
|
gid=100
|
||||||
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
|
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:52:35
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -28,4 +28,4 @@ simplex iterations : 2663
|
||||||
flow value : 3080014995
|
flow value : 3080014995
|
||||||
checksum : 68389
|
checksum : 68389
|
||||||
optimal
|
optimal
|
||||||
Exiting @ tick 382091472000 because target called exit()
|
Exiting @ tick 382077495000 because target called exit()
|
||||||
|
|
|
@ -1,82 +1,82 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 855655 # Simulator instruction rate (inst/s)
|
host_inst_rate 1204056 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 331116 # Number of bytes of host memory used
|
host_mem_usage 359708 # Number of bytes of host memory used
|
||||||
host_seconds 315.19 # Real time elapsed on the host
|
host_seconds 223.99 # Real time elapsed on the host
|
||||||
host_tick_rate 1212247082 # Simulator tick rate (ticks/s)
|
host_tick_rate 1705780609 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 269695959 # Number of instructions simulated
|
sim_insts 269696010 # Number of instructions simulated
|
||||||
sim_seconds 0.382091 # Number of seconds simulated
|
sim_seconds 0.382077 # Number of seconds simulated
|
||||||
sim_ticks 382091472000 # Number of ticks simulated
|
sim_ticks 382077495000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 15892.729148 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 15892.283447 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12892.729148 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12892.283447 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_hits 88818985 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_miss_latency 31157028000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 31160318000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.021596 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_misses 1960458 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 25275654000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 25278158000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021596 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1960458 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000.038268 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000.038318 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.038268 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.038318 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_hits 31204566 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 31204877 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_miss_latency 13170313000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 13152953000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.007480 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.007471 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_misses 235184 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 234874 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 12464761000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 12448331000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007480 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007471 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 235184 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 234874 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_refs 58.134189 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_avg_miss_latency 20188.783508 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 20182.816586 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 17182.816586 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_hits 120023551 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 120023607 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_miss_latency 44327341000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 44313271000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_rate 0.017965 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.017964 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_misses 2195642 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 2195594 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 37740415000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 37726489000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.017965 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.017964 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_misses 2195642 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 2195594 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.occ_%::0 0.995395 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_%::0 0.995398 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.occ_blocks::0 4077.137530 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4077.149063 # Average occupied blocks per context
|
||||||
system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_avg_miss_latency 20188.783508 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 20182.816586 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 17188.783508 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 17182.816586 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_hits 120023551 # number of overall hits
|
system.cpu.dcache.overall_hits 120023607 # number of overall hits
|
||||||
system.cpu.dcache.overall_miss_latency 44327341000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 44313271000 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_rate 0.017965 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.017964 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_misses 2195642 # number of overall misses
|
system.cpu.dcache.overall_misses 2195594 # number of overall misses
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 37740415000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 37726489000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.017965 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.017964 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_misses 2195642 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 2195594 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.replacements 2062715 # number of replacements
|
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||||
system.cpu.dcache.sampled_refs 2066811 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.tagsinuse 4077.137530 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4077.149063 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 120152382 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 127457925000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 127446193000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.writebacks 235136 # number of writebacks
|
system.cpu.dcache.writebacks 234826 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_accesses 217696172 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_hits 217695364 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
||||||
|
@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms
|
||||||
system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_refs 269424.955446 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 217696172 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 217695364 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
||||||
|
@ -105,13 +105,13 @@ system.cpu.icache.demand_mshr_misses 808 # nu
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.325918 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.325920 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 667.480800 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 667.483560 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 217695364 # number of overall hits
|
system.cpu.icache.overall_hits 217695401 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 808 # number of overall misses
|
system.cpu.icache.overall_misses 808 # number of overall misses
|
||||||
|
@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
||||||
system.cpu.icache.replacements 24 # number of replacements
|
system.cpu.icache.replacements 24 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 667.480800 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 667.483560 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 217695364 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.l2cache.ReadExReq_accesses 106353 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.291482 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.292152 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 5530387000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 5517699000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 106353 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 106109 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4254120000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4244360000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 106353 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 106109 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 1961266 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 1872110 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1872381 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 4636112000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 4635644000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.045458 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.045448 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 89156 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 89147 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3566240000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 3565880000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045458 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.045448 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 89156 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 89147 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 128831 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 128765 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51991.120150 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51991.115598 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 6698068000 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 6694636000 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 128831 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 128765 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5153240000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 5150600000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 128831 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 128765 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.Writeback_accesses 235136 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 234826 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_hits 235136 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 234826 # number of Writeback hits
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 13.775269 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 13.775827 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 2067619 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000.158560 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52000.158766 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 1872110 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1872381 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 10166499000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 10153343000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.094558 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.094434 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 195509 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 195256 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 7820360000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 7810240000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.094558 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.094434 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 195509 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 195256 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.198854 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.198864 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_%::1 0.350512 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::1 0.350544 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 6516.062046 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 6516.387210 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 11485.589337 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 11486.611177 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 2067619 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000.158560 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000.158766 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 1872110 # number of overall hits
|
system.cpu.l2cache.overall_hits 1872381 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 10166499000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 10153343000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.094558 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.094434 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 195509 # number of overall misses
|
system.cpu.l2cache.overall_misses 195256 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 7820360000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 7810240000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.094558 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.094434 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 195509 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 195256 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 109056 # number of replacements
|
system.cpu.l2cache.replacements 109048 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 132990 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 132982 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 18001.651383 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 18002.998387 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1831973 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1831937 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 70891 # number of writebacks
|
system.cpu.l2cache.writebacks 70890 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 764182944 # number of cpu cycles simulated
|
system.cpu.numCycles 764154990 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 269695959 # Number of instructions executed
|
system.cpu.num_insts 269696010 # Number of instructions executed
|
||||||
system.cpu.num_refs 122219131 # Number of memory references
|
system.cpu.num_refs 122219139 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -57,9 +57,9 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
|
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||||
gid=100
|
gid=100
|
||||||
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
|
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:53:46
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -74,4 +74,4 @@ info: Increasing stack size by one page.
|
||||||
about 2 million people attended
|
about 2 million people attended
|
||||||
the five best costumes got prizes
|
the five best costumes got prizes
|
||||||
No errors!
|
No errors!
|
||||||
Exiting @ tick 868585211000 because target called exit()
|
Exiting @ tick 868585242000 because target called exit()
|
||||||
|
|
|
@ -1,18 +1,18 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 1408369 # Simulator instruction rate (inst/s)
|
host_inst_rate 3246924 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 192628 # Number of bytes of host memory used
|
host_mem_usage 221228 # Number of bytes of host memory used
|
||||||
host_seconds 1062.01 # Real time elapsed on the host
|
host_seconds 460.65 # Real time elapsed on the host
|
||||||
host_tick_rate 817869724 # Simulator tick rate (ticks/s)
|
host_tick_rate 1885557129 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 1495700470 # Number of instructions simulated
|
sim_insts 1495700521 # Number of instructions simulated
|
||||||
sim_seconds 0.868585 # Number of seconds simulated
|
sim_seconds 0.868585 # Number of seconds simulated
|
||||||
sim_ticks 868585211000 # Number of ticks simulated
|
sim_ticks 868585242000 # Number of ticks simulated
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 1737170423 # number of cpu cycles simulated
|
system.cpu.numCycles 1737170485 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 1495700470 # Number of instructions executed
|
system.cpu.num_insts 1495700521 # Number of instructions executed
|
||||||
system.cpu.num_refs 533262337 # Number of memory references
|
system.cpu.num_refs 533262345 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -157,9 +157,9 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/parser
|
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||||
gid=100
|
gid=100
|
||||||
input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/parser/mdred/input/parser.in
|
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
output=cout
|
output=cout
|
||||||
pid=100
|
pid=100
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:54:07
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -74,4 +74,4 @@ info: Increasing stack size by one page.
|
||||||
about 2 million people attended
|
about 2 million people attended
|
||||||
the five best costumes got prizes
|
the five best costumes got prizes
|
||||||
No errors!
|
No errors!
|
||||||
Exiting @ tick 1722331568000 because target called exit()
|
Exiting @ tick 1722332515000 because target called exit()
|
||||||
|
|
|
@ -1,82 +1,82 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 925832 # Simulator instruction rate (inst/s)
|
host_inst_rate 1698687 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 200280 # Number of bytes of host memory used
|
host_mem_usage 228888 # Number of bytes of host memory used
|
||||||
host_seconds 1615.52 # Real time elapsed on the host
|
host_seconds 880.50 # Real time elapsed on the host
|
||||||
host_tick_rate 1066115675 # Simulator tick rate (ticks/s)
|
host_tick_rate 1956075066 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 1495700470 # Number of instructions simulated
|
sim_insts 1495700521 # Number of instructions simulated
|
||||||
sim_seconds 1.722332 # Number of seconds simulated
|
sim_seconds 1.722333 # Number of seconds simulated
|
||||||
sim_ticks 1722331568000 # Number of ticks simulated
|
sim_ticks 1722332515000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 24153.691272 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 24152.982435 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21153.690114 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21152.981277 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_hits 382374810 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_miss_latency 41722410000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 41722200000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_misses 1727372 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 36540292000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 36539956000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 1727372 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.912307 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 55999.911625 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912307 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.911625 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_hits 147694869 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 147694849 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_miss_latency 82058407500 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 82059582500 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.009824 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_misses 1465331 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1465352 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 77662414500 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 77663526500 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009824 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1465331 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 1465352 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_refs 210.745406 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_avg_miss_latency 38769.912986 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 38769.450220 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_hits 530069679 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 530069624 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_miss_latency 123780817500 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 123781782500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.005987 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_misses 3192703 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 3192766 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 114202706500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 114203482500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.005987 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_misses 3192703 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 3192766 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.occ_%::0 0.997757 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_%::0 0.997759 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.occ_blocks::0 4086.814341 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4086.820737 # Average occupied blocks per context
|
||||||
system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_avg_miss_latency 38769.912986 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 38769.450220 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35769.912360 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 35769.449593 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_hits 530069679 # number of overall hits
|
system.cpu.dcache.overall_hits 530069624 # number of overall hits
|
||||||
system.cpu.dcache.overall_miss_latency 123780817500 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 123781782500 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.005987 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_misses 3192703 # number of overall misses
|
system.cpu.dcache.overall_misses 3192766 # number of overall misses
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 114202706500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 114203482500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.005987 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_misses 3192703 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 3192766 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.replacements 2514317 # number of replacements
|
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||||
system.cpu.dcache.sampled_refs 2518413 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.tagsinuse 4086.814341 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4086.820737 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 530743969 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 8217895000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 8218050000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.writebacks 1463113 # number of writebacks
|
system.cpu.dcache.writebacks 1463134 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_accesses 1068347073 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_hits 1068344259 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 136836000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
|
||||||
|
@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # ms
|
||||||
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 48626.865672 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 1068344259 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 136836000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
|
||||||
|
@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.433368 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 887.538461 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 887.538061 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 48626.865672 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 1068344259 # number of overall hits
|
system.cpu.icache.overall_hits 1068344296 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 136836000 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 2814 # number of overall misses
|
system.cpu.icache.overall_misses 2814 # number of overall misses
|
||||||
|
@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
||||||
system.cpu.icache.replacements 1253 # number of replacements
|
system.cpu.icache.replacements 1253 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 887.538461 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 887.538061 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 1068344259 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.l2cache.ReadExReq_accesses 791041 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014538 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 41134143500 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 41134299500 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 791041 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 791044 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641640000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31641760000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 791041 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 791044 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 1730186 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 1310266 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1310327 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 21835840000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 21834852000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.242702 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.242685 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 419920 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 419901 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 16796800000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 16796040000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242702 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242685 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 419920 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 419901 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 674290 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 674308 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.203458 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.126631 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 35055800000 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 35056684000 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 674290 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 674308 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26971600000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26972320000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 674290 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 674308 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.Writeback_accesses 1463113 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 1463134 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_hits 1463113 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 1463134 # number of Writeback hits
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 3.423900 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 3.424249 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 2521227 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52000.009497 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 1310266 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1310327 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 62969983500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 62969151500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.480306 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.480291 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 1210961 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 1210945 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 48438440000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 48437800000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.480306 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.480291 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 1210961 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 1210945 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.111890 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.111884 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_%::1 0.413414 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::1 0.413412 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 3666.426168 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 3666.207378 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 13546.751396 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 13546.690457 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 2521227 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000.009497 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 1310266 # number of overall hits
|
system.cpu.l2cache.overall_hits 1310327 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 62969983500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 62969151500 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.480306 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.480291 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 1210961 # number of overall misses
|
system.cpu.l2cache.overall_misses 1210945 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 48438440000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 48437800000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.480306 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.480291 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 1210961 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 1210945 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 664073 # number of replacements
|
system.cpu.l2cache.replacements 664035 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 680479 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 680440 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 17213.177564 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 17212.897835 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 2329892 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 2329996 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 921652677000 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 921653687000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 481653 # number of writebacks
|
system.cpu.l2cache.writebacks 481618 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 3444663136 # number of cpu cycles simulated
|
system.cpu.numCycles 3444665030 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 1495700470 # Number of instructions executed
|
system.cpu.num_insts 1495700521 # Number of instructions executed
|
||||||
system.cpu.num_refs 533262337 # Number of memory references
|
system.cpu.num_refs 533262345 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -57,7 +57,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2
|
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:57:51
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -29,4 +29,4 @@ Uncompressing Data
|
||||||
Uncompressed data 1048576 bytes in length
|
Uncompressed data 1048576 bytes in length
|
||||||
Uncompressed data compared correctly
|
Uncompressed data compared correctly
|
||||||
Tested 1MB buffer: OK!
|
Tested 1MB buffer: OK!
|
||||||
Exiting @ tick 2829239875500 because target called exit()
|
Exiting @ tick 2829239906500 because target called exit()
|
||||||
|
|
|
@ -1,18 +1,18 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 1880958 # Simulator instruction rate (inst/s)
|
host_inst_rate 2905658 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 188832 # Number of bytes of host memory used
|
host_mem_usage 217444 # Number of bytes of host memory used
|
||||||
host_seconds 2473.91 # Real time elapsed on the host
|
host_seconds 1601.47 # Real time elapsed on the host
|
||||||
host_tick_rate 1143628848 # Simulator tick rate (ticks/s)
|
host_tick_rate 1766650252 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 4653327894 # Number of instructions simulated
|
sim_insts 4653327945 # Number of instructions simulated
|
||||||
sim_seconds 2.829240 # Number of seconds simulated
|
sim_seconds 2.829240 # Number of seconds simulated
|
||||||
sim_ticks 2829239875500 # Number of ticks simulated
|
sim_ticks 2829239906500 # Number of ticks simulated
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 5658479752 # number of cpu cycles simulated
|
system.cpu.numCycles 5658479814 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 4653327894 # Number of instructions executed
|
system.cpu.num_insts 4653327945 # Number of instructions executed
|
||||||
system.cpu.num_refs 1677713078 # Number of memory references
|
system.cpu.num_refs 1677713086 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -157,7 +157,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/bzip2
|
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 03:58:19
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
@ -29,4 +29,4 @@ Uncompressing Data
|
||||||
Uncompressed data 1048576 bytes in length
|
Uncompressed data 1048576 bytes in length
|
||||||
Uncompressed data compared correctly
|
Uncompressed data compared correctly
|
||||||
Tested 1MB buffer: OK!
|
Tested 1MB buffer: OK!
|
||||||
Exiting @ tick 5988037845000 because target called exit()
|
Exiting @ tick 5988071419000 because target called exit()
|
||||||
|
|
|
@ -1,82 +1,82 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 1049992 # Simulator instruction rate (inst/s)
|
host_inst_rate 1729585 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 196480 # Number of bytes of host memory used
|
host_mem_usage 225072 # Number of bytes of host memory used
|
||||||
host_seconds 4431.78 # Real time elapsed on the host
|
host_seconds 2690.43 # Real time elapsed on the host
|
||||||
host_tick_rate 1351159917 # Simulator tick rate (ticks/s)
|
host_tick_rate 2225692892 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 4653327894 # Number of instructions simulated
|
sim_insts 4653327945 # Number of instructions simulated
|
||||||
sim_seconds 5.988038 # Number of seconds simulated
|
sim_seconds 5.988071 # Number of seconds simulated
|
||||||
sim_ticks 5988037845000 # Number of ticks simulated
|
sim_ticks 5988071419000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 25018.463901 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 25017.777193 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22018.463901 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.777193 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_hits 1231962487 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_miss_latency 180689726000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 180699652000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.005828 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_misses 7222255 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 159022961000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 159031102000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005828 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 7222255 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_accesses 438528336 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.840680 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 55999.839821 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.840680 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839821 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_hits 436281288 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 436280849 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_miss_latency 125834330000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 125858968000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.005124 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.005125 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_misses 2247048 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 2247488 # number of WriteReq misses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119093186000 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency 119116504000 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005125 # mshr miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 2247048 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 2247488 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_refs 183.121439 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_avg_miss_latency 32370.287021 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 32370.399029 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_hits 1668243775 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 1668242748 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_miss_latency 306524056000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 306558620000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_rate 0.005644 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.005645 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_misses 9469303 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 9470338 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 278116147000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 278147606000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.005644 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.005645 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_misses 9469303 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 9470338 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.occ_%::0 0.997259 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_%::0 0.997262 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.occ_blocks::0 4084.774232 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 4084.783575 # Average occupied blocks per context
|
||||||
system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_avg_miss_latency 32370.287021 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 32370.399029 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29370.287021 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_hits 1668243775 # number of overall hits
|
system.cpu.dcache.overall_hits 1668242748 # number of overall hits
|
||||||
system.cpu.dcache.overall_miss_latency 306524056000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 306558620000 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_rate 0.005644 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_misses 9469303 # number of overall misses
|
system.cpu.dcache.overall_misses 9470338 # number of overall misses
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 278116147000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 278147606000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.005644 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_misses 9469303 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 9470338 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.replacements 9107896 # number of replacements
|
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||||
system.cpu.dcache.sampled_refs 9111992 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.tagsinuse 4084.774232 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 4084.783575 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 1668601086 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 58863918000 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 58864073000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.writebacks 2243955 # number of writebacks
|
system.cpu.dcache.writebacks 2244395 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_accesses 4013232890 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_hits 4013232215 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
|
||||||
|
@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms
|
||||||
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_refs 5945529.207407 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 4013232890 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 4013232215 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
|
||||||
|
@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 555.573148 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 555.572992 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 4013232215 # number of overall hits
|
system.cpu.icache.overall_hits 4013232252 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 675 # number of overall misses
|
system.cpu.icache.overall_misses 675 # number of overall misses
|
||||||
|
@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
||||||
system.cpu.icache.replacements 10 # number of replacements
|
system.cpu.icache.replacements 10 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 555.573148 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 555.572992 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 4013232215 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.l2cache.ReadExReq_accesses 1889737 # number of ReadExReq accesses(hits+misses)
|
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency 98266324000 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency 98271004000 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_misses 1889737 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses 1889827 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75589480000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75593080000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889737 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 1889827 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 7222930 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 5327537 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 5328094 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 98560436000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 98562412000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.262413 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.262397 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 1895393 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 1895431 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 75815720000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 75817240000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262413 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262397 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 1895393 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 1895431 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 357311 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 357661 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.899729 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.659935 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency 18561556000 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency 18579652000 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_misses 357311 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses 357661 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14292440000 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14306440000 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 357311 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 357661 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.Writeback_accesses 2243955 # number of Writeback accesses(hits+misses)
|
system.cpu.l2cache.Writeback_accesses 2244395 # number of Writeback accesses(hits+misses)
|
||||||
system.cpu.l2cache.Writeback_hits 2243955 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 2244395 # number of Writeback hits
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 2.380966 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 2.381264 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 9112667 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 5327537 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 5328094 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 196826760000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 196833416000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.415370 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.415353 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 3785130 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 3785258 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 151405200000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 151410320000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415370 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.415353 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 3785130 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 3785258 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.437806 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.437808 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_%::1 0.347809 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::1 0.347808 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 14346.014207 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 14346.083027 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 11397.001683 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 11396.963852 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 9112667 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 5327537 # number of overall hits
|
system.cpu.l2cache.overall_hits 5328094 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 196826760000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 196833416000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.415370 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.415353 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 3785130 # number of overall misses
|
system.cpu.l2cache.overall_misses 3785258 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 151405200000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 151410320000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415370 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.415353 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 3785130 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 3785258 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 2771977 # number of replacements
|
system.cpu.l2cache.replacements 2772035 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 2798150 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 2798208 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 25743.015890 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 25743.046878 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 6662299 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 6663271 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 4737770578000 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 4737794502000 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 1199166 # number of writebacks
|
system.cpu.l2cache.writebacks 1199204 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 11976075690 # number of cpu cycles simulated
|
system.cpu.numCycles 11976142838 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 4653327894 # Number of instructions executed
|
system.cpu.num_insts 4653327945 # Number of instructions executed
|
||||||
system.cpu.num_refs 1677713078 # Number of memory references
|
system.cpu.num_refs 1677713086 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -57,7 +57,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
|
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,11 +5,13 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 04:02:03
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
|
||||||
|
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
|
||||||
|
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -27,4 +29,4 @@ info: Increasing stack size by one page.
|
||||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||||
122 123 124 Exiting @ tick 130427072000 because target called exit()
|
122 123 124 Exiting @ tick 130427103000 because target called exit()
|
||||||
|
|
|
@ -1,18 +1,18 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 1408387 # Simulator instruction rate (inst/s)
|
host_inst_rate 1941332 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 196212 # Number of bytes of host memory used
|
host_mem_usage 224824 # Number of bytes of host memory used
|
||||||
host_seconds 155.80 # Real time elapsed on the host
|
host_seconds 113.03 # Real time elapsed on the host
|
||||||
host_tick_rate 837126295 # Simulator tick rate (ticks/s)
|
host_tick_rate 1153901611 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 219430973 # Number of instructions simulated
|
sim_insts 219431024 # Number of instructions simulated
|
||||||
sim_seconds 0.130427 # Number of seconds simulated
|
sim_seconds 0.130427 # Number of seconds simulated
|
||||||
sim_ticks 130427072000 # Number of ticks simulated
|
sim_ticks 130427103000 # Number of ticks simulated
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 260854145 # number of cpu cycles simulated
|
system.cpu.numCycles 260854207 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 219430973 # Number of instructions executed
|
system.cpu.num_insts 219431024 # Number of instructions executed
|
||||||
system.cpu.num_refs 77165298 # Number of memory references
|
system.cpu.num_refs 77165306 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -157,7 +157,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/twolf
|
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,11 +5,13 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 04:04:39
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
|
||||||
|
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
|
||||||
|
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
|
|
||||||
|
@ -27,4 +29,4 @@ info: Increasing stack size by one page.
|
||||||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||||
122 123 124 Exiting @ tick 250962019000 because target called exit()
|
122 123 124 Exiting @ tick 250962187000 because target called exit()
|
||||||
|
|
|
@ -1,27 +1,27 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 527252 # Simulator instruction rate (inst/s)
|
host_inst_rate 1720597 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 203888 # Number of bytes of host memory used
|
host_mem_usage 232456 # Number of bytes of host memory used
|
||||||
host_seconds 416.18 # Real time elapsed on the host
|
host_seconds 127.53 # Real time elapsed on the host
|
||||||
host_tick_rate 603014388 # Simulator tick rate (ticks/s)
|
host_tick_rate 1967834922 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 219430973 # Number of instructions simulated
|
sim_insts 219431024 # Number of instructions simulated
|
||||||
sim_seconds 0.250962 # Number of seconds simulated
|
sim_seconds 0.250962 # Number of seconds simulated
|
||||||
sim_ticks 250962019000 # Number of ticks simulated
|
sim_ticks 250962187000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 56682001 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 55228.395062 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52226.851852 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_hits 56681677 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_miss_latency 17894000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_misses 324 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16921500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_hits 20514125 # number of WriteReq hits
|
system.cpu.dcache.WriteReq_hits 20514126 # number of WriteReq hits
|
||||||
system.cpu.dcache.WriteReq_miss_latency 89824000 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency 89824000 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
|
||||||
system.cpu.dcache.WriteReq_misses 1604 # number of WriteReq misses
|
system.cpu.dcache.WriteReq_misses 1604 # number of WriteReq misses
|
||||||
|
@ -30,53 +30,53 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # m
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 1604 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 1604 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_refs 40586.660358 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.demand_accesses 77197730 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_avg_miss_latency 55870.331950 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 55848.783014 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52870.072614 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_hits 77195802 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 77195807 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_miss_latency 107718000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 107844000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_misses 1928 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 1931 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 101933500 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 102050500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_misses 1928 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 1931 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.occ_%::0 0.332384 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_%::0 0.332873 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.occ_blocks::0 1361.446792 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 1363.445907 # Average occupied blocks per context
|
||||||
system.cpu.dcache.overall_accesses 77197730 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_avg_miss_latency 55870.331950 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 55848.783014 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52870.072614 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_hits 77195802 # number of overall hits
|
system.cpu.dcache.overall_hits 77195807 # number of overall hits
|
||||||
system.cpu.dcache.overall_miss_latency 107718000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 107844000 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_misses 1928 # number of overall misses
|
system.cpu.dcache.overall_misses 1931 # number of overall misses
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 101933500 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 102050500 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_misses 1928 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 1931 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.replacements 40 # number of replacements
|
system.cpu.dcache.replacements 41 # number of replacements
|
||||||
system.cpu.dcache.sampled_refs 1902 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.tagsinuse 1361.446792 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 1363.445907 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 77195828 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.writebacks 7 # number of writebacks
|
system.cpu.dcache.writebacks 7 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_accesses 173494375 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_hits 173489681 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
|
||||||
|
@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # ms
|
||||||
system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_refs 36959.880912 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 173494375 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 173489681 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
|
||||||
|
@ -105,13 +105,13 @@ system.cpu.icache.demand_mshr_misses 4694 # nu
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.710588 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.710587 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 1455.283940 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 1455.283090 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 173494375 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 173489681 # number of overall hits
|
system.cpu.icache.overall_hits 173489718 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 4694 # number of overall misses
|
system.cpu.icache.overall_misses 4694 # number of overall misses
|
||||||
|
@ -124,8 +124,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
|
||||||
system.cpu.icache.replacements 2836 # number of replacements
|
system.cpu.icache.replacements 2836 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 1455.283940 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 1455.283090 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 173489681 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
@ -138,16 +138,16 @@ system.cpu.l2cache.ReadExReq_misses 1578 # nu
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63120000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 1578 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 5018 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52004.908170 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 1860 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 164231500 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.629334 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 3158 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 126320000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629334 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 3158 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
@ -161,55 +161,55 @@ system.cpu.l2cache.Writeback_accesses 7 # nu
|
||||||
system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 0.593112 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.593053 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 6596 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52003.272804 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52003.271423 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 1860 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1861 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 246287500 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 246391500 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.718011 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.717988 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 4736 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 4738 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 189440000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 189520000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.718011 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.717988 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 4736 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 4738 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.062047 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.062108 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 2033.146081 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 2035.144824 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.occ_blocks::1 0.022985 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::1 0.021758 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 6596 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52003.272804 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 1860 # number of overall hits
|
system.cpu.l2cache.overall_hits 1861 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 246287500 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 246391500 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.718011 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.717988 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 4736 # number of overall misses
|
system.cpu.l2cache.overall_misses 4738 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 189440000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 189520000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.718011 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.717988 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 4736 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 4738 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 3136 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 3138 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 2033.169065 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 2035.166582 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1860 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 501924038 # number of cpu cycles simulated
|
system.cpu.numCycles 501924374 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 219430973 # Number of instructions executed
|
system.cpu.num_insts 219431024 # Number of instructions executed
|
||||||
system.cpu.num_refs 77165298 # Number of memory references
|
system.cpu.num_refs 77165306 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -57,7 +57,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
|
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 04:11:29
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Hello world!
|
Hello world!
|
||||||
Exiting @ tick 5504000 because target called exit()
|
Exiting @ tick 5526500 because target called exit()
|
||||||
|
|
|
@ -1,18 +1,18 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 940985 # Simulator instruction rate (inst/s)
|
host_inst_rate 940026 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 185436 # Number of bytes of host memory used
|
host_mem_usage 213000 # Number of bytes of host memory used
|
||||||
host_seconds 0.01 # Real time elapsed on the host
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
host_tick_rate 530148334 # Simulator tick rate (ticks/s)
|
host_tick_rate 529916579 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 9519 # Number of instructions simulated
|
sim_insts 9561 # Number of instructions simulated
|
||||||
sim_seconds 0.000006 # Number of seconds simulated
|
sim_seconds 0.000006 # Number of seconds simulated
|
||||||
sim_ticks 5504000 # Number of ticks simulated
|
sim_ticks 5526500 # Number of ticks simulated
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 11009 # number of cpu cycles simulated
|
system.cpu.numCycles 11054 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 9519 # Number of instructions executed
|
system.cpu.num_insts 9561 # Number of instructions executed
|
||||||
system.cpu.num_refs 1987 # Number of memory references
|
system.cpu.num_refs 1990 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
@ -157,7 +157,7 @@ egid=100
|
||||||
env=
|
env=
|
||||||
errout=cerr
|
errout=cerr
|
||||||
euid=100
|
euid=100
|
||||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
|
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||||
gid=100
|
gid=100
|
||||||
input=cin
|
input=cin
|
||||||
max_stack_size=67108864
|
max_stack_size=67108864
|
||||||
|
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
||||||
All Rights Reserved
|
All Rights Reserved
|
||||||
|
|
||||||
|
|
||||||
M5 compiled Feb 25 2010 03:41:05
|
M5 compiled May 2 2010 23:23:01
|
||||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
|
||||||
M5 started Feb 25 2010 04:11:30
|
M5 started May 2 2010 23:23:02
|
||||||
M5 executing on SC2B0619
|
M5 executing on burrito
|
||||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
|
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
|
||||||
Global frequency set at 1000000000000 ticks per second
|
Global frequency set at 1000000000000 ticks per second
|
||||||
info: Entering event queue @ 0. Starting simulation...
|
info: Entering event queue @ 0. Starting simulation...
|
||||||
Hello world!
|
Hello world!
|
||||||
Exiting @ tick 29731000 because target called exit()
|
Exiting @ tick 29813000 because target called exit()
|
||||||
|
|
|
@ -1,23 +1,23 @@
|
||||||
|
|
||||||
---------- Begin Simulation Statistics ----------
|
---------- Begin Simulation Statistics ----------
|
||||||
host_inst_rate 605496 # Simulator instruction rate (inst/s)
|
host_inst_rate 734670 # Simulator instruction rate (inst/s)
|
||||||
host_mem_usage 193040 # Number of bytes of host memory used
|
host_mem_usage 220588 # Number of bytes of host memory used
|
||||||
host_seconds 0.02 # Real time elapsed on the host
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
host_tick_rate 1857026858 # Simulator tick rate (ticks/s)
|
host_tick_rate 2255655595 # Simulator tick rate (ticks/s)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
sim_insts 9519 # Number of instructions simulated
|
sim_insts 9561 # Number of instructions simulated
|
||||||
sim_seconds 0.000030 # Number of seconds simulated
|
sim_seconds 0.000030 # Number of seconds simulated
|
||||||
sim_ticks 29731000 # Number of ticks simulated
|
sim_ticks 29813000 # Number of ticks simulated
|
||||||
system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits
|
system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
|
||||||
system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||||
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||||
|
@ -30,102 +30,102 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # m
|
||||||
system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
|
system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks.
|
system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
|
||||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses
|
system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
|
||||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits
|
system.cpu.dcache.demand_hits 1837 # number of demand (read+write) hits
|
||||||
system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency 8568000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses
|
system.cpu.dcache.demand_miss_rate 0.076884 # miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses
|
system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
|
||||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency 8109000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses
|
system.cpu.dcache.demand_mshr_miss_rate 0.076884 # mshr miss rate for demand accesses
|
||||||
system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dcache.occ_%::0 0.019744 # Average percentage of cache occupancy
|
system.cpu.dcache.occ_%::0 0.019841 # Average percentage of cache occupancy
|
||||||
system.cpu.dcache.occ_blocks::0 80.872189 # Average occupied blocks per context
|
system.cpu.dcache.occ_blocks::0 81.267134 # Average occupied blocks per context
|
||||||
system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
|
system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
|
||||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_hits 1835 # number of overall hits
|
system.cpu.dcache.overall_hits 1837 # number of overall hits
|
||||||
system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency 8568000 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate 0.076884 # miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_misses 152 # number of overall misses
|
system.cpu.dcache.overall_misses 153 # number of overall misses
|
||||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency 8109000 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate 0.076884 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.replacements 0 # number of replacements
|
system.cpu.dcache.replacements 0 # number of replacements
|
||||||
system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
|
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.dcache.tagsinuse 80.872189 # Cycle average of tags in use
|
system.cpu.dcache.tagsinuse 81.267134 # Cycle average of tags in use
|
||||||
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
|
system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
|
||||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||||
system.cpu.icache.ReadReq_accesses 6887 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_hits 6659 # number of ReadReq hits
|
system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
|
||||||
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_rate 0.033106 # miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
|
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.033106 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
|
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
|
||||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.icache.avg_refs 29.206140 # Average number of references to valid blocks.
|
system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.icache.demand_accesses 6887 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
|
||||||
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_hits 6659 # number of demand (read+write) hits
|
system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
|
||||||
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_rate 0.033106 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
|
||||||
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
|
||||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_rate 0.033106 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.occ_%::0 0.052069 # Average percentage of cache occupancy
|
system.cpu.icache.occ_%::0 0.052030 # Average percentage of cache occupancy
|
||||||
system.cpu.icache.occ_blocks::0 106.638328 # Average occupied blocks per context
|
system.cpu.icache.occ_blocks::0 106.557747 # Average occupied blocks per context
|
||||||
system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses
|
system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
|
||||||
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_hits 6659 # number of overall hits
|
system.cpu.icache.overall_hits 6683 # number of overall hits
|
||||||
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_rate 0.033106 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_misses 228 # number of overall misses
|
system.cpu.icache.overall_misses 228 # number of overall misses
|
||||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_rate 0.033106 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.replacements 0 # number of replacements
|
system.cpu.icache.replacements 0 # number of replacements
|
||||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.icache.tagsinuse 106.638328 # Cycle average of tags in use
|
system.cpu.icache.tagsinuse 106.557747 # Cycle average of tags in use
|
||||||
system.cpu.icache.total_refs 6659 # Total number of references to valid blocks.
|
system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
|
||||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.icache.writebacks 0 # number of writebacks
|
system.cpu.icache.writebacks 0 # number of writebacks
|
||||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||||
|
@ -138,16 +138,16 @@ system.cpu.l2cache.ReadExReq_misses 79 # nu
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||||
system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||||
|
@ -159,53 +159,53 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||||
system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks.
|
system.cpu.l2cache.avg_refs 0.003802 # Average number of references to valid blocks.
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||||
system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses
|
system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
|
||||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.occ_%::0 0.003910 # Average percentage of cache occupancy
|
system.cpu.l2cache.occ_%::0 0.003920 # Average percentage of cache occupancy
|
||||||
system.cpu.l2cache.occ_blocks::0 128.120518 # Average occupied blocks per context
|
system.cpu.l2cache.occ_blocks::0 128.459536 # Average occupied blocks per context
|
||||||
system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
|
system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
|
||||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||||
system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_misses 360 # number of overall misses
|
system.cpu.l2cache.overall_misses 361 # number of overall misses
|
||||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.replacements 0 # number of replacements
|
system.cpu.l2cache.replacements 0 # number of replacements
|
||||||
system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
|
system.cpu.l2cache.sampled_refs 263 # Sample count of references to valid blocks.
|
||||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||||
system.cpu.l2cache.tagsinuse 128.120518 # Cycle average of tags in use
|
system.cpu.l2cache.tagsinuse 128.459536 # Cycle average of tags in use
|
||||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||||
system.cpu.numCycles 59462 # number of cpu cycles simulated
|
system.cpu.numCycles 59626 # number of cpu cycles simulated
|
||||||
system.cpu.num_insts 9519 # Number of instructions executed
|
system.cpu.num_insts 9561 # Number of instructions executed
|
||||||
system.cpu.num_refs 1987 # Number of memory references
|
system.cpu.num_refs 1990 # Number of memory references
|
||||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
Loading…
Reference in a new issue