ARM: Support forcing load/store multiple to use user registers.
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bb903b6514
commit
8a4af3668d
4 changed files with 32 additions and 26 deletions
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@ -90,27 +90,14 @@ class ArmMacroMemoryOp : public PredMacroOp
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uint32_t reglist;
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uint32_t reglist;
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uint32_t ones;
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uint32_t ones;
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uint32_t puswl,
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prepost,
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up,
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psruser,
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writeback,
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loadop;
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ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
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ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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OpClass __opClass)
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: PredMacroOp(mnem, _machInst, __opClass),
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: PredMacroOp(mnem, _machInst, __opClass), memAccessFlags(0),
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memAccessFlags(0),
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reglist(machInst.regList), ones(0)
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reglist(machInst.regList), ones(0),
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puswl(machInst.puswl),
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prepost(machInst.puswl.prepost),
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up(machInst.puswl.up),
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psruser(machInst.puswl.psruser),
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writeback(machInst.puswl.writeback),
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loadop(machInst.puswl.loadOp)
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{
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{
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ones = number_of_ones(reglist);
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ones = number_of_ones(reglist);
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numMicroops = ones + writeback + 1;
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numMicroops = ones + machInst.puswl.writeback + 1;
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// Remember that writeback adds a uop
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// Remember that writeback adds a uop
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microOps = new StaticInstPtr[numMicroops];
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microOps = new StaticInstPtr[numMicroops];
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}
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}
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@ -324,6 +324,13 @@ INTREG_FIQ(unsigned index)
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return IntRegFiqMap[index];
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return IntRegFiqMap[index];
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}
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}
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static inline IntRegIndex
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intRegForceUser(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return (IntRegIndex)(index + NUM_INTREGS);
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}
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}
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}
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#endif
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#endif
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@ -125,8 +125,11 @@ namespace ArmISA
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assert(reg >= 0);
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assert(reg >= 0);
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if (reg < NUM_ARCH_INTREGS) {
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if (reg < NUM_ARCH_INTREGS) {
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return intRegMap[reg];
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return intRegMap[reg];
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} else if (reg < NUM_INTREGS) {
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return reg;
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} else {
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} else {
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assert(reg < NUM_INTREGS);
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reg -= NUM_INTREGS;
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assert(reg < NUM_ARCH_INTREGS);
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return reg;
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return reg;
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}
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}
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}
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}
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@ -180,11 +180,12 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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%(constructor)s;
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%(constructor)s;
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uint32_t regs = reglist;
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uint32_t regs = reglist;
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uint32_t addr = 0;
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uint32_t addr = 0;
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bool up = machInst.puswl.up;
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if (!up)
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if (!up)
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addr = (ones << 2) - 4;
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addr = (ones << 2) - 4;
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if (prepost)
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if (machInst.puswl.prepost)
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addr += 4;
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addr += 4;
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// Add 0 to Rn and stick it in ureg0.
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// Add 0 to Rn and stick it in ureg0.
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@ -198,10 +199,18 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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reg++;
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reg++;
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replaceBits(regs, reg, 0);
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replaceBits(regs, reg, 0);
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if (loadop)
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unsigned regIdx = reg;
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microOps[i] = new MicroLdrUop(machInst, reg, INTREG_UREG0, addr);
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if (machInst.puswl.psruser) {
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else
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regIdx = intRegForceUser(regIdx);
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microOps[i] = new MicroStrUop(machInst, reg, INTREG_UREG0, addr);
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}
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if (machInst.puswl.loadOp) {
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microOps[i] =
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new MicroLdrUop(machInst, regIdx, INTREG_UREG0, addr);
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} else {
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microOps[i] =
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new MicroStrUop(machInst, regIdx, INTREG_UREG0, addr);
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}
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if (up)
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if (up)
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addr += 4;
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addr += 4;
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@ -210,7 +219,7 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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}
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}
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StaticInstPtr &lastUop = microOps[numMicroops - 1];
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StaticInstPtr &lastUop = microOps[numMicroops - 1];
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if (writeback) {
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if (machInst.puswl.writeback) {
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if (up) {
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if (up) {
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lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
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lastUop = new MicroAddiUop(machInst, RN, RN, ones * 4);
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} else {
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} else {
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