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ARM: Allow access to the RGNR register.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:10 -05:00
parent c3381167c9
commit 89b1dd5582
1 changed files with 2 additions and 3 deletions
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5
src/arch/arm/miscregs.hh
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@ -104,6 +104,7 @@ namespace ArmISA
MISCREG_BPIALL, MISCREG_BPIALL,
MISCREG_MPUIR, MISCREG_MPUIR,
MISCREG_MIDR, MISCREG_MIDR,
MISCREG_RGNR,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -136,7 +137,6 @@ namespace ArmISA
MISCREG_IRSR, MISCREG_IRSR,
MISCREG_DRACR, MISCREG_DRACR,
MISCREG_IRACR, MISCREG_IRACR,
MISCREG_RGNR,
MISCREG_DCIMVAC, MISCREG_DCIMVAC,
MISCREG_DCISW, MISCREG_DCISW,
MISCREG_MCCSW, MISCREG_MCCSW,
@ -164,14 +164,13 @@ namespace ArmISA
"clidr", "ccsidr", "csselr", "clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau", "icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall", "bpimva", "bpiallis", "bpiall",
"mpuir", "midr", "ctr", "tcmtr", "mpidr", "mpuir", "midr", "rgnr", "ctr", "tcmtr", "mpidr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"aidr", "actlr", "aidr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr",
"dcimvac", "dcisw", "mccsw", "dcimvac", "dcisw", "mccsw",
"dccmvau", "dccmvau",
"nop", "raz" "nop", "raz"