Just give up if a store conditional misses completely

in the cache (don't treat as normal write miss).

--HG--
extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74

src/mem/cache/cache_impl.hh

@@ -231,8 +231,11 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
                 exitSimLoop("A cache reached the maximum miss count");
         }
     }
+
+    if (!(pkt->flags & SATISFIED)) {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
-//    return MA_CACHE_MISS;
+    }
+
     return true;
 }
 
@@ -585,7 +588,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
             assert(pkt->result == Packet::Success);
         }
         return 0;
-    } else if (!blk) {
+    } else if (!blk && !(pkt->flags & SATISFIED)) {
         // update the cache state and statistics
         if (mshr || !writes.empty()){
             // Can't handle it, return pktuest unsatisfied.
@@ -653,6 +656,7 @@ return 0;
             return memSidePort->sendAtomic(pkt);
         }
     } else {
+        if (blk) {
             // There was a cache hit.
             // Handle writebacks if needed
             while (!writebacks.empty()){
@@ -661,10 +665,11 @@ return 0;
             }
 
             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+        }
 
         return hitLatency;
     }
-    fatal("Probe not handled.\n");
+
     return 0;
 }