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Just give up if a store conditional misses completely

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in the cache (don't treat as normal write miss).

--HG--
extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74
This commit is contained in:
Steve Reinhardt 2006-10-21 17:19:33 -07:00
parent 82e90bf5e0
commit 883ed108e4
1 changed files with 16 additions and 11 deletions
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11
src/mem/cache/cache_impl.hh vendored
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@ -231,8 +231,11 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
exitSimLoop("A cache reached the maximum miss count"); exitSimLoop("A cache reached the maximum miss count");
} }
} }
if (!(pkt->flags & SATISFIED)) {
missQueue->handleMiss(pkt, size, curTick + hitLatency); missQueue->handleMiss(pkt, size, curTick + hitLatency);
// return MA_CACHE_MISS; }
return true; return true;
} }
@ -585,7 +588,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
assert(pkt->result == Packet::Success); assert(pkt->result == Packet::Success);
} }
return 0; return 0;
} else if (!blk) { } else if (!blk && !(pkt->flags & SATISFIED)) {
// update the cache state and statistics // update the cache state and statistics
if (mshr || !writes.empty()){ if (mshr || !writes.empty()){
// Can't handle it, return pktuest unsatisfied. // Can't handle it, return pktuest unsatisfied.
@ -653,6 +656,7 @@ return 0;
return memSidePort->sendAtomic(pkt); return memSidePort->sendAtomic(pkt);
} }
} else { } else {
if (blk) {
// There was a cache hit. // There was a cache hit.
// Handle writebacks if needed // Handle writebacks if needed
while (!writebacks.empty()){ while (!writebacks.empty()){
@ -661,10 +665,11 @@ return 0;
} }
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
}
return hitLatency; return hitLatency;
} }
fatal("Probe not handled.\n");
return 0; return 0;
} }