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test: Restore eio ref files clobbered in rev 8800b05e1cb3.

Browse source 
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
This commit is contained in:
Steve Reinhardt 2012-07-23 00:33:05 -04:00
parent 2590a7dd0a
commit 882a4b65bd
12 changed files with 2416 additions and 48 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
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@ -1,9 +1,6 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> warn: Prefetch instructions in Alpha do not do anything
File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main warn: Prefetch instructions in Alpha do not do anything
exec filecode in scope hack: be nice to actually delete the event here
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, mode, name, 'test.py')) gzip: stdout: Broken pipe
File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined

11
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
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@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31 gem5 compiled Feb 29 2012 00:47:21
gem5 started May 8 2012 15:37:08 gem5 started Feb 29 2012 00:51:57
gem5 executing on piton gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 250015500 because a thread reached the max instruction count

80
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
View file

@ -0,0 +1,80 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3174528 # Simulator instruction rate (inst/s)
host_op_rate 3174125 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1586983445 # Simulator tick rate (ticks/s)
host_mem_usage 203780 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2872676 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2000076 # Number of instructions bytes read from this memory
system.physmem.bytes_written 417562 # Number of bytes written to this memory
system.physmem.num_reads 624454 # Number of read requests responded to by this memory
system.physmem.num_writes 56340 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 11489991621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 7999808012 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 1670144451 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 13160136072 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.itb.fetch_hits 500019 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 500032 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 500032 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu.num_func_calls 14357 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu.num_int_insts 474689 # number of integer instructions
system.cpu.num_fp_insts 32 # number of float instructions
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 180793 # number of memory refs
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 500032 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------

15
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
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@ -1,9 +1,6 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> warn: Prefetch instructions in Alpha do not do anything
File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main warn: Prefetch instructions in Alpha do not do anything
exec filecode in scope hack: be nice to actually delete the event here
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, mode, name, 'test.py')) gzip: stdout: Broken pipe
File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
root.system.cpu.workload = EioProcess(file = binpath('anagram',
NameError: name 'EioProcess' is not defined

11
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
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@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31 gem5 compiled Feb 29 2012 00:47:21
gem5 started May 8 2012 15:37:07 gem5 started Feb 29 2012 00:51:57
gem5 executing on piton gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
>Exiting @ tick 727929000 because a thread reached the max instruction count

330
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
View file

@ -0,0 +1,330 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000728 # Number of seconds simulated
sim_ticks 727929000 # Number of ticks simulated
final_tick 727929000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1742138 # Simulator instruction rate (inst/s)
host_op_rate 1742023 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2535976572 # Simulator tick rate (ticks/s)
host_mem_usage 212652 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
sim_insts 500001 # Number of instructions simulated
sim_ops 500001 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 54848 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25792 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 857 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 75348008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 35432027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 75348008 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 124435 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 124443 # DTB read accesses
system.cpu.dtb.write_hits 56340 # DTB write hits
system.cpu.dtb.write_misses 10 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 56350 # DTB write accesses
system.cpu.dtb.data_hits 180775 # DTB hits
system.cpu.dtb.data_misses 18 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 180793 # DTB accesses
system.cpu.itb.fetch_hits 500020 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 500033 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 1455858 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 500001 # Number of instructions committed
system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu.num_func_calls 14357 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu.num_int_insts 474689 # number of integer instructions
system.cpu.num_fp_insts 32 # number of float instructions
system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_mem_refs 180793 # number of memory refs
system.cpu.num_load_insts 124443 # Number of load instructions
system.cpu.num_store_insts 56350 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1455858 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 264.952126 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.129371 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.129371 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 499617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 499617 # number of overall hits
system.cpu.icache.overall_hits::total 499617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 403 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.icache.overall_misses::total 403 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 22568000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 22568000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 22568000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 22568000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 22568000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000806 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 403 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 403 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21359000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 287.175167 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.070111 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
system.cpu.dcache.overall_hits::total 180321 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.dcache.overall_misses::total 454 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 17640000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 17640000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7784000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7784000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 25424000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 25424000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 25424000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 25424000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7367000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7367000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24062000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 24062000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 24062000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 264.958770 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 216.460700 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.008086 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006606 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.014692 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 139 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 403 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 454 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 857 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 403 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 454 # number of overall misses
system.cpu.l2cache.overall_misses::total 857 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20956000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16380000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 37336000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7228000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7228000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 20956000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 23608000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 44564000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 20956000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 23608000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 44564000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 403 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 315 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 139 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 403 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 454 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 857 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 403 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 454 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 857 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 403 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 718 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 139 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 403 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 403 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 857 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12600000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5560000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16120000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16120000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34280000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

19
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
View file

@ -1,9 +1,10 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> warn: Prefetch instructions in Alpha do not do anything
File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main warn: Prefetch instructions in Alpha do not do anything
exec filecode in scope hack: be nice to actually delete the event here
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, mode, name, 'test.py')) gzip: stdout: Broken pipe
File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) gzip: stdout: Broken pipe
NameError: name 'EioProcess' is not defined
gzip: stdout: Broken pipe

17
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
View file

@ -1,7 +1,18 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31 gem5 compiled Feb 29 2012 00:47:21
gem5 started May 8 2012 15:40:55 gem5 started Feb 29 2012 00:51:57
gem5 executing on piton gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 250015500 because a thread reached the max instruction count

749
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
View file

@ -0,0 +1,749 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000250 # Number of seconds simulated
sim_ticks 250015500 # Number of ticks simulated
final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3384594 # Simulator instruction rate (inst/s)
host_op_rate 3384489 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 423074550 # Simulator tick rate (ticks/s)
host_mem_usage 1140672 # Number of bytes of host memory used
host_seconds 0.59 # Real time elapsed on the host
sim_insts 2000004 # Number of instructions simulated
sim_ops 2000004 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 219392 # Number of bytes read from this memory
system.physmem.bytes_inst_read 103168 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 3428 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 877513594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 412646416 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 877513594 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 124435 # DTB read hits
system.cpu0.dtb.read_misses 8 # DTB read misses
system.cpu0.dtb.read_acv 0 # DTB read access violations
system.cpu0.dtb.read_accesses 124443 # DTB read accesses
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
system.cpu0.dtb.write_acv 0 # DTB write access violations
system.cpu0.dtb.write_accesses 56350 # DTB write accesses
system.cpu0.dtb.data_hits 180775 # DTB hits
system.cpu0.dtb.data_misses 18 # DTB misses
system.cpu0.dtb.data_acv 0 # DTB access violations
system.cpu0.dtb.data_accesses 180793 # DTB accesses
system.cpu0.itb.fetch_hits 500019 # ITB hits
system.cpu0.itb.fetch_misses 13 # ITB misses
system.cpu0.itb.fetch_acv 0 # ITB acv
system.cpu0.itb.fetch_accesses 500032 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu0.numCycles 500032 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu0.num_func_calls 14357 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu0.num_int_insts 474689 # number of integer instructions
system.cpu0.num_fp_insts 32 # number of float instructions
system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu0.num_mem_refs 180793 # number of memory refs
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_busy_cycles 500032 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 152 # number of replacements
system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
system.cpu0.icache.overall_hits::total 499556 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 61 # number of replacements
system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu0.dcache.writebacks::total 29 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 124435 # DTB read hits
system.cpu1.dtb.read_misses 8 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
system.cpu1.dtb.write_hits 56340 # DTB write hits
system.cpu1.dtb.write_misses 10 # DTB write misses
system.cpu1.dtb.write_acv 0 # DTB write access violations
system.cpu1.dtb.write_accesses 56350 # DTB write accesses
system.cpu1.dtb.data_hits 180775 # DTB hits
system.cpu1.dtb.data_misses 18 # DTB misses
system.cpu1.dtb.data_acv 0 # DTB access violations
system.cpu1.dtb.data_accesses 180793 # DTB accesses
system.cpu1.itb.fetch_hits 500019 # ITB hits
system.cpu1.itb.fetch_misses 13 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_accesses 500032 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.workload.num_syscalls 18 # Number of system calls
system.cpu1.numCycles 500032 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 500001 # Number of instructions committed
system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu1.num_int_insts 474689 # number of integer instructions
system.cpu1.num_fp_insts 32 # number of float instructions
system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu1.num_mem_refs 180793 # number of memory refs
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_store_insts 56350 # Number of store instructions
system.cpu1.num_idle_cycles 0 # Number of idle cycles
system.cpu1.num_busy_cycles 500032 # Number of busy cycles
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0 # Percentage of idle cycles
system.cpu1.icache.replacements 152 # number of replacements
system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
system.cpu1.icache.overall_hits::total 499556 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
system.cpu1.icache.overall_misses::total 463 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 61 # number of replacements
system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits
system.cpu1.dcache.overall_hits::total 180312 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu1.dcache.writebacks::total 29 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 124435 # DTB read hits
system.cpu2.dtb.read_misses 8 # DTB read misses
system.cpu2.dtb.read_acv 0 # DTB read access violations
system.cpu2.dtb.read_accesses 124443 # DTB read accesses
system.cpu2.dtb.write_hits 56340 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
system.cpu2.dtb.write_acv 0 # DTB write access violations
system.cpu2.dtb.write_accesses 56350 # DTB write accesses
system.cpu2.dtb.data_hits 180775 # DTB hits
system.cpu2.dtb.data_misses 18 # DTB misses
system.cpu2.dtb.data_acv 0 # DTB access violations
system.cpu2.dtb.data_accesses 180793 # DTB accesses
system.cpu2.itb.fetch_hits 500019 # ITB hits
system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.fetch_acv 0 # ITB acv
system.cpu2.itb.fetch_accesses 500032 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.workload.num_syscalls 18 # Number of system calls
system.cpu2.numCycles 500032 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 500001 # Number of instructions committed
system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu2.num_int_insts 474689 # number of integer instructions
system.cpu2.num_fp_insts 32 # number of float instructions
system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu2.num_mem_refs 180793 # number of memory refs
system.cpu2.num_load_insts 124443 # Number of load instructions
system.cpu2.num_store_insts 56350 # Number of store instructions
system.cpu2.num_idle_cycles 0 # Number of idle cycles
system.cpu2.num_busy_cycles 500032 # Number of busy cycles
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu2.idle_fraction 0 # Percentage of idle cycles
system.cpu2.icache.replacements 152 # number of replacements
system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
system.cpu2.icache.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
system.cpu2.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
system.cpu2.icache.overall_hits::total 499556 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
system.cpu2.icache.overall_misses::total 463 # number of overall misses
system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 61 # number of replacements
system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
system.cpu2.dcache.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
system.cpu2.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits
system.cpu2.dcache.overall_hits::total 180312 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu2.dcache.writebacks::total 29 # number of writebacks
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dtb.fetch_hits 0 # ITB hits
system.cpu3.dtb.fetch_misses 0 # ITB misses
system.cpu3.dtb.fetch_acv 0 # ITB acv
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
system.cpu3.dtb.read_hits 124435 # DTB read hits
system.cpu3.dtb.read_misses 8 # DTB read misses
system.cpu3.dtb.read_acv 0 # DTB read access violations
system.cpu3.dtb.read_accesses 124443 # DTB read accesses
system.cpu3.dtb.write_hits 56340 # DTB write hits
system.cpu3.dtb.write_misses 10 # DTB write misses
system.cpu3.dtb.write_acv 0 # DTB write access violations
system.cpu3.dtb.write_accesses 56350 # DTB write accesses
system.cpu3.dtb.data_hits 180775 # DTB hits
system.cpu3.dtb.data_misses 18 # DTB misses
system.cpu3.dtb.data_acv 0 # DTB access violations
system.cpu3.dtb.data_accesses 180793 # DTB accesses
system.cpu3.itb.fetch_hits 500019 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.fetch_acv 0 # ITB acv
system.cpu3.itb.fetch_accesses 500032 # ITB accesses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.read_acv 0 # DTB read access violations
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.itb.write_acv 0 # DTB write access violations
system.cpu3.itb.write_accesses 0 # DTB write accesses
system.cpu3.itb.data_hits 0 # DTB hits
system.cpu3.itb.data_misses 0 # DTB misses
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
system.cpu3.workload.num_syscalls 18 # Number of system calls
system.cpu3.numCycles 500032 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.committedInsts 500001 # Number of instructions committed
system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed
system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls
system.cpu3.num_int_insts 474689 # number of integer instructions
system.cpu3.num_fp_insts 32 # number of float instructions
system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read
system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu3.num_mem_refs 180793 # number of memory refs
system.cpu3.num_load_insts 124443 # Number of load instructions
system.cpu3.num_store_insts 56350 # Number of store instructions
system.cpu3.num_idle_cycles 0 # Number of idle cycles
system.cpu3.num_busy_cycles 500032 # Number of busy cycles
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
system.cpu3.icache.replacements 152 # number of replacements
system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
system.cpu3.icache.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
system.cpu3.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
system.cpu3.icache.overall_hits::total 499556 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
system.cpu3.icache.overall_misses::total 463 # number of overall misses
system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 61 # number of replacements
system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
system.cpu3.dcache.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
system.cpu3.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits
system.cpu3.dcache.overall_hits::total 180312 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
system.cpu3.dcache.writebacks::total 29 # number of writebacks
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.029950 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 276 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

19
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
View file

@ -1,9 +1,10 @@
Traceback (most recent call last): warn: Sockets disabled, not accepting gdb connections
File "<string>", line 1, in <module> warn: Prefetch instructions in Alpha do not do anything
File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main warn: Prefetch instructions in Alpha do not do anything
exec filecode in scope hack: be nice to actually delete the event here
File "tests/run.py", line 78, in <module>
execfile(joinpath(tests_root, category, mode, name, 'test.py')) gzip: stdout: Broken pipe
File "tests/quick/se/30.eio-mp/test.py", line 29, in <module>
process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) gzip: stdout: Broken pipe
NameError: name 'EioProcess' is not defined
gzip: stdout: Broken pipe

17
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
View file

@ -1,7 +1,18 @@
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 8 2012 15:36:31 gem5 compiled Feb 29 2012 00:47:21
gem5 started May 8 2012 15:36:56 gem5 started Feb 29 2012 00:51:57
gem5 executing on piton gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
>>>>Exiting @ tick 728920000 because a thread reached the max instruction count

1181
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
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