I missed a couple of WithEffects, this should do it
--HG-- extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
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2f7a4e1d1b
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87fb0eb8de
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@ -1368,7 +1368,7 @@ class ControlRegOperand(Operand):
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bit_select = 0
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bit_select = 0
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if (self.ctype == 'float' or self.ctype == 'double'):
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if (self.ctype == 'float' or self.ctype == 'double'):
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error(0, 'Attempt to read control register as FP')
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error(0, 'Attempt to read control register as FP')
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base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx
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base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
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if self.size == self.dflt_size:
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if self.size == self.dflt_size:
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return '%s = %s;\n' % (self.base_name, base)
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return '%s = %s;\n' % (self.base_name, base)
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else:
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else:
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@ -1378,7 +1378,7 @@ class ControlRegOperand(Operand):
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def makeWrite(self):
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def makeWrite(self):
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if (self.ctype == 'float' or self.ctype == 'double'):
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if (self.ctype == 'float' or self.ctype == 'double'):
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error(0, 'Attempt to write control register as FP')
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error(0, 'Attempt to write control register as FP')
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wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \
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wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \
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(self.dest_reg_idx, self.base_name)
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(self.dest_reg_idx, self.base_name)
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wb += 'if (traceData) { traceData->setData(%s); }' % \
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wb += 'if (traceData) { traceData->setData(%s); }' % \
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self.base_name
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self.base_name
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@ -374,7 +374,7 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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case MISCREG_HPSTATE:
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case MISCREG_HPSTATE:
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return readFSRegWithEffect(miscReg, tc);
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return readFSReg(miscReg, tc);
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#else
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#else
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case MISCREG_HPSTATE:
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case MISCREG_HPSTATE:
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//HPSTATE is special because because sometimes in privilege checks for instructions
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//HPSTATE is special because because sometimes in privilege checks for instructions
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@ -682,7 +682,7 @@ void MiscRegFile::setReg(int miscReg,
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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case MISCREG_HPSTATE:
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case MISCREG_HPSTATE:
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setFSRegWithEffect(miscReg, val, tc);
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setFSReg(miscReg, val, tc);
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return;
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return;
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#else
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#else
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case MISCREG_HPSTATE:
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case MISCREG_HPSTATE:
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@ -257,9 +257,8 @@ namespace SparcISA
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// These need to check the int_dis field and if 0 then
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// These need to check the int_dis field and if 0 then
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// set appropriate bit in softint and checkinterrutps on the cpu
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// set appropriate bit in softint and checkinterrutps on the cpu
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void setFSRegWithEffect(int miscReg, const MiscReg &val,
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void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
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ThreadContext *tc);
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MiscReg readFSReg(int miscReg, ThreadContext * tc);
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MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
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// Update interrupt state on softint or pil change
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// Update interrupt state on softint or pil change
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void checkSoftInt(ThreadContext *tc);
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void checkSoftInt(ThreadContext *tc);
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@ -59,8 +59,7 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
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void
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void
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MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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ThreadContext *tc)
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{
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{
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int64_t time;
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int64_t time;
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switch (miscReg) {
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switch (miscReg) {
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@ -196,7 +195,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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}
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}
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MiscReg
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MiscReg
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MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
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MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
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{
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{
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switch (miscReg) {
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switch (miscReg) {
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/* Privileged registers. */
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/* Privileged registers. */
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@ -125,7 +125,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
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}
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}
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/** Reads a miscellaneous register. */
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/** Reads a miscellaneous register. */
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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{
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return this->cpu->readMiscRegNoEffect(
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return this->cpu->readMiscRegNoEffect(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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@ -135,7 +135,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
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/** Reads a misc. register, including any side-effects the read
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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* might have as defined by the architecture.
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*/
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*/
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TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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{
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return this->cpu->readMiscReg(
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return this->cpu->readMiscReg(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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@ -143,7 +143,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
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}
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}
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/** Sets a misc. register. */
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/** Sets a misc. register. */
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void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
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void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
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{
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{
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this->instResult.integer = val;
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this->instResult.integer = val;
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return this->cpu->setMiscRegNoEffect(
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return this->cpu->setMiscRegNoEffect(
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@ -154,7 +154,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
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/** Sets a misc. register, including any side-effects the write
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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* might have as defined by the architecture.
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*/
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*/
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void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
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void setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val)
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const MiscReg &val)
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{
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{
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return this->cpu->setMiscReg(
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return this->cpu->setMiscReg(
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@ -107,7 +107,7 @@ class SparcDynInst : public BaseDynInst<Impl>
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}
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}
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/** Reads a miscellaneous register. */
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/** Reads a miscellaneous register. */
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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{
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return this->cpu->readMiscRegNoEffect(
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return this->cpu->readMiscRegNoEffect(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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@ -117,7 +117,7 @@ class SparcDynInst : public BaseDynInst<Impl>
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/** Reads a misc. register, including any side-effects the read
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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* might have as defined by the architecture.
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*/
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*/
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TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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{
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return this->cpu->readMiscReg(
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return this->cpu->readMiscReg(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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@ -125,7 +125,7 @@ class SparcDynInst : public BaseDynInst<Impl>
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}
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}
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/** Sets a misc. register. */
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/** Sets a misc. register. */
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void setMiscRegOperand(const StaticInst * si,
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void setMiscRegOperandNoEffect(const StaticInst * si,
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int idx, const TheISA::MiscReg &val)
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int idx, const TheISA::MiscReg &val)
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{
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{
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this->instResult.integer = val;
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this->instResult.integer = val;
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@ -137,7 +137,7 @@ class SparcDynInst : public BaseDynInst<Impl>
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/** Sets a misc. register, including any side-effects the write
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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* might have as defined by the architecture.
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*/
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*/
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void setMiscRegOperandWithEffect(
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void setMiscRegOperand(
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const StaticInst *si, int idx, const TheISA::MiscReg &val)
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const StaticInst *si, int idx, const TheISA::MiscReg &val)
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{
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{
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return this->cpu->setMiscReg(
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return this->cpu->setMiscReg(
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@ -304,25 +304,25 @@ class BaseSimpleCPU : public BaseCPU
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return thread->setMiscReg(misc_reg, val);
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return thread->setMiscReg(misc_reg, val);
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}
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}
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MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->readMiscRegNoEffect(reg_idx);
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return thread->readMiscRegNoEffect(reg_idx);
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}
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}
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MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
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MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->readMiscReg(reg_idx);
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return thread->readMiscReg(reg_idx);
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}
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}
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void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
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void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
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{
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->setMiscRegNoEffect(reg_idx, val);
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return thread->setMiscRegNoEffect(reg_idx, val);
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}
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}
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void setMiscRegOperandWithEffect(
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void setMiscRegOperand(
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const StaticInst *si, int idx, const MiscReg &val)
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const StaticInst *si, int idx, const MiscReg &val)
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{
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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