sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

ARM: Implement the SADD8 and SADD16 instructions.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:06 -05:00
parent d70c31437a
commit 87975aa691
1 changed files with 37 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

39
src/arch/arm/isa/insts/data.isa
View file

@ -73,6 +73,7 @@ let {{
"llbit": (oldC, oldC, oldC), "llbit": (oldC, oldC, oldC),
"saturate": ('0', '0', '0'), "saturate": ('0', '0', '0'),
"overflow": ('0', '0', '0'), "overflow": ('0', '0', '0'),
"ge": ('0', '0', '0'),
"add": ('findCarry(32, resTemp, Op1, secondOp)', "add": ('findCarry(32, resTemp, Op1, secondOp)',
'findCarry(32, resTemp, Op1, secondOp)', 'findCarry(32, resTemp, Op1, secondOp)',
'findCarry(32, resTemp, Op1, secondOp)'), 'findCarry(32, resTemp, Op1, secondOp)'),
@ -92,6 +93,7 @@ let {{
"llbit": oldV, "llbit": oldV,
"saturate": '0', "saturate": '0',
"overflow": '0', "overflow": '0',
"ge": '0',
"add": 'findOverflow(32, resTemp, Op1, secondOp)', "add": 'findOverflow(32, resTemp, Op1, secondOp)',
"sub": 'findOverflow(32, resTemp, Op1, ~secondOp)', "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
"rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)', "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
@ -150,7 +152,7 @@ let {{
if flagType == "saturate": if flagType == "saturate":
regCcCode = calcQCode regCcCode = calcQCode
elif flagType == "ge": elif flagType == "ge":
immCcCode = calcGECode regCcCode = calcGECode
else: else:
regCcCode = calcCcCode % { regCcCode = calcCcCode % {
"icValue": secondOpRe.sub(regOp2, cCode[1]), "icValue": secondOpRe.sub(regOp2, cCode[1]),
@ -188,7 +190,7 @@ let {{
if flagType == "saturate": if flagType == "saturate":
regRegCcCode = calcQCode regRegCcCode = calcQCode
elif flagType == "ge": elif flagType == "ge":
immCcCode = calcGECode regRegCcCode = calcGECode
else: else:
regRegCcCode = calcCcCode % { regRegCcCode = calcCcCode % {
"icValue": secondOpRe.sub(regRegOp2, cCode[2]), "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
@ -360,4 +362,37 @@ let {{
replaceBits(resTemp, 31, 16, midRes); replaceBits(resTemp, 31, 16, midRes);
Dest = resTemp; Dest = resTemp;
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("sadd8", '''
uint32_t geBits = 0;
resTemp = 0;
for (unsigned i = 0; i < 4; i++) {
int high = (i + 1) * 8 - 1;
int low = i * 8;
int32_t midRes = sext<8>(bits(Op1, high, low)) +
sext<8>(bits(Op2, high, low));
replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) {
geBits = geBits | (1 << i);
}
}
Dest = resTemp;
resTemp = geBits;
''', flagType="ge", buildNonCc=False)
buildRegDataInst("sadd16", '''
uint32_t geBits = 0;
resTemp = 0;
for (unsigned i = 0; i < 2; i++) {
int high = (i + 1) * 16 - 1;
int low = i * 16;
int32_t midRes = sext<16>(bits(Op1, high, low)) +
sext<16>(bits(Op2, high, low));
replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) {
geBits = geBits | (0x3 << (i * 2));
}
}
Dest = resTemp;
resTemp = geBits;
''', flagType="ge", buildNonCc=False)
}}; }};