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test, arm: Add scripts to test checkpoints

Browse source 
Add a set of scripts to automatically test checkpointing in the
regression framework. The checkpointing tests are similar to the
switcheroo tests, but instead of switching between CPUs, they
checkpoint the system and restore from the checkpoint again. This is
done at regular intervals, typically while booting Linux.

The implementation is fairly straight forward, with the exception that
we have to work around gem5's inability to restore from a checkpoint
after a system has been instantiated. We work around this by forking
off child processes that does the actual simulation and never
instantiate a system in the parent process unless a maximum checkpoint
count is reached (in which case we just simulate the system to
completion in the parent).

Checkpoint testing is currently only enabled 32- and 64-bit ARM
systems using atomic CPUs.

Note: An unfortunate side-effect of forking is that every new process
will overwrite the stats and terminal output from the previous
process. This means that the output directory only contains data from
the last checkpoint.
This commit is contained in:
Andreas Sandberg 2015-03-19 04:06:20 -04:00
parent ecd4bad351
commit 877435950c
12 changed files with 7721 additions and 0 deletions
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2
tests/SConscript
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@ -322,6 +322,7 @@ if env['TARGET_ISA'] == 'arm':
'o3-timing-checker', 'o3-timing-checker',
'realview-simple-atomic', 'realview-simple-atomic',
'realview-simple-atomic-dual', 'realview-simple-atomic-dual',
'realview-simple-atomic-checkpoint',
'realview-simple-timing', 'realview-simple-timing',
'realview-simple-timing-dual', 'realview-simple-timing-dual',
'realview-o3', 'realview-o3',
@ -334,6 +335,7 @@ if env['TARGET_ISA'] == 'arm':
'realview-switcheroo-o3', 'realview-switcheroo-o3',
'realview-switcheroo-full', 'realview-switcheroo-full',
'realview64-simple-atomic', 'realview64-simple-atomic',
'realview64-simple-atomic-checkpoint',
'realview64-simple-atomic-dual', 'realview64-simple-atomic-dual',
'realview64-simple-timing', 'realview64-simple-timing',
'realview64-simple-timing-dual', 'realview64-simple-timing-dual',

133
tests/configs/checkpoint.py Normal file
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@ -0,0 +1,133 @@
# Copyright (c) 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
from multiprocessing import Process
import sys
import os
import m5
m5.util.addToPath('../configs/common')
_exit_normal = (
"target called exit()",
"m5_exit instruction encountered",
)
_exit_limit = (
"simulate() limit reached",
)
_exitcode_done = 0
_exitcode_fail = 1
_exitcode_checkpoint = 42
def _run_step(name, restore=None, interval=0.5):
"""
Instantiate (optionally from a checkpoint if restore is set to the
checkpoitn name) the system and run for interval seconds of
simulated time. At the end of the simulation interval, create a
checkpoint and exit.
As this function is intended to run in its own process using the
multiprocessing framework, the exit is a true call to exit which
terminates the process. Exit codes are used to pass information to
the parent.
"""
if restore is not None:
m5.instantiate(restore)
else:
m5.instantiate()
e = m5.simulate(m5.ticks.fromSeconds(interval))
cause = e.getCause()
if cause in _exit_limit:
m5.checkpoint(name)
sys.exit(_exitcode_checkpoint)
elif cause in _exit_normal:
sys.exit(_exitcode_done)
else:
print "Test failed: Unknown exit cause: %s" % cause
sys.exit(_exitcode_fail)
def run_test(root, interval=0.5, max_checkpoints=5):
"""
Run the simulated system for a fixed amount of time and take a
checkpoint, then restore from the same checkpoint and run until
the system calls m5 exit.
"""
cpt_name = os.path.join(m5.options.outdir, "test.cpt")
restore = None
for cpt_no in range(max_checkpoints):
# Create a checkpoint from a separate child process. This enables
# us to get back to a (mostly) pristine state and restart
# simulation from the checkpoint.
p = Process(target=_run_step,
args=(cpt_name, ),
kwargs={
"restore" : restore,
"interval" : interval,
})
p.start()
# Wait for the child to return
p.join()
# Restore from the checkpoint next iteration
restore = cpt_name
if p.exitcode == _exitcode_done:
print >> sys.stderr, "Test done."
sys.exit(0)
elif p.exitcode == _exitcode_checkpoint:
pass
else:
print >> sys.stderr, "Test failed."
sys.exit(1)
# Maximum number of checkpoints reached. Just run full-speed from
# now on.
m5.instantiate()
e = m5.simulate()
cause = e.getCause()
if cause in _exit_normal:
sys.exit(0)
else:
print "Test failed: Unknown exit cause: %s" % cause
sys.exit(1)

46
tests/configs/realview-simple-atomic-checkpoint.py Normal file
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@ -0,0 +1,46 @@
# Copyright (c) 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
from m5.objects import *
from arm_generic import *
import checkpoint
root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
run_test = checkpoint.run_test

50
tests/configs/realview64-simple-atomic-checkpoint.py Normal file
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@ -0,0 +1,50 @@
# Copyright (c) 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
import functools
from m5.objects import *
from arm_generic import *
import checkpoint
root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
mem_mode='atomic',
mem_class=SimpleMemory,
cpu_class=AtomicSimpleCPU).create_root()
run_test = functools.partial(checkpoint.run_test, interval=1.0)

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tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini Normal file
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tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json Normal file
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tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt Normal file
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@ -0,0 +1,781 @@
---------- Begin Simulation Statistics ----------
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate 904753 # Simulator instruction rate (inst/s)
host_mem_usage 665260 # Number of bytes of host memory used
host_op_rate 1063233 # Simulator op (including micro ops) rate (op/s)
host_seconds 1088.22 # Real time elapsed on the host
host_tick_rate 46967646801 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
sim_seconds 51.111153 # Number of seconds simulated
sim_ticks 51111152682000 # Number of ticks simulated
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.clk_domain.clock 1000 # Clock period in ticks
system.cpu.Branches 220088562 # Number of branches fetched
system.cpu.committedInsts 984570519 # Number of instructions committed
system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses
system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits
system.cpu.dcache.overall_hits::total 331514149 # number of overall hits
system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses
system.cpu.dcache.overall_misses::total 10164734 # number of overall misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements 11612141 # number of replacements
system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks
system.cpu.dcache.writebacks::total 8921315 # number of writebacks
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dtb.accesses 352512518 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 352246803 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 265715 # DTB misses
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 184208233 # DTB read accesses
system.cpu.dtb.read_hits 184014035 # DTB read hits
system.cpu.dtb.read_misses 194198 # DTB read misses
system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walks 265715 # Table walker walks requested
system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
system.cpu.dtb.write_accesses 168304285 # DTB write accesses
system.cpu.dtb.write_hits 168232768 # DTB write hits
system.cpu.dtb.write_misses 71517 # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits
system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits
system.cpu.icache.overall_hits::total 970865862 # number of overall hits
system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses
system.cpu.icache.overall_misses::total 14296158 # number of overall misses
system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements 14295641 # number of replacements
system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.itb.accesses 985174158 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 985047321 # DTB hits
system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
system.cpu.itb.inst_hits 985047321 # ITB inst hits
system.cpu.itb.inst_misses 126837 # ITB inst misses
system.cpu.itb.misses 126837 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walks 126837 # Table walker walks requested
system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses
system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses
system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits
system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses
system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements 1722692 # number of replacements
system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks
system.cpu.l2cache.writebacks::total 1503415 # number of writebacks
system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
system.cpu.numCycles 102222322140 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
system.cpu.num_fp_insts 880805 # number of float instructions
system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
system.cpu.num_func_calls 57056367 # number of times a function call or return occured
system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
system.cpu.num_int_insts 1060455466 # number of integer instructions
system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
system.cpu.num_load_insts 184180431 # Number of load instructions
system.cpu.num_mem_refs 352465606 # number of memory refs
system.cpu.num_store_insts 168285175 # Number of store instructions
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1157666593 # Class of executed instruction
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8817 # number of overall misses
system.iocache.overall_misses::total 8857 # number of overall misses
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.data_accesses 1039686 # Number of data accesses
system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.replacements 115463 # number of replacements
system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3583537 # Request fanout histogram
system.membus.snoops 0 # Total snoops (count)
system.membus.trans_dist::ReadReq 526062 # Transaction distribution
system.membus.trans_dist::ReadResp 526062 # Transaction distribution
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
system.membus.trans_dist::Writeback 1610046 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.voltage_domain.voltage 1 # Voltage in Volts
---------- End Simulation Statistics ----------

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[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
[ 0.000000] Memory limited to 256MB
[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
[ 0.000000] On node 0 totalpages: 65536
[ 0.000000] DMA zone: 896 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000013] Console: colour dummy device 80x25
[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000015] pid_max: default: 32768 minimum: 301
[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000066] hw perfevents: no hardware support available
[ 1.060049] CPU1: failed to come online
[ 2.080098] CPU2: failed to come online
[ 3.100148] CPU3: failed to come online
[ 3.100150] Brought up 1 CPUs
[ 3.100151] SMP: Total of 1 processors activated.
[ 3.100177] devtmpfs: initialized
[ 3.100579] atomic64_test: passed
[ 3.100603] regulator-dummy: no parameters
[ 3.100844] NET: Registered protocol family 16
[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.100981] Serial: AMBA PL011 UART driver
[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.101160] console [ttyAMA0] enabled
[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130356] 3V3: 3300 mV
[ 3.130377] vgaarb: loaded
[ 3.130406] SCSI subsystem initialized
[ 3.130425] libata version 3.00 loaded.
[ 3.130450] usbcore: registered new interface driver usbfs
[ 3.130457] usbcore: registered new interface driver hub
[ 3.130471] usbcore: registered new device driver usb
[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.130487] PTP clock support registered
[ 3.130559] Switched to clocksource arch_sys_counter
[ 3.131204] NET: Registered protocol family 2
[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.131263] TCP: reno registered
[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131281] NET: Registered protocol family 1
[ 3.131310] RPC: Registered named UNIX socket transport module.
[ 3.131311] RPC: Registered udp transport module.
[ 3.131312] RPC: Registered tcp transport module.
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.131315] PCI: CLS 0 bytes, default 64
[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.132687] fuse init (API version 7.23)
[ 3.132738] msgmni has been set to 469
[ 3.133992] io scheduler noop registered
[ 3.134024] io scheduler cfq registered (default)
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.134302] pci_bus 0000:00: scanning bus
[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134354] pci_bus 0000:00: fixups for bus
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.134813] ata_piix 0000:00:01.0: version 2.13
[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.135009] scsi0 : ata_piix
[ 3.135063] scsi1 : ata_piix
[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290572] ata1.00: configured for UDMA/33
[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.290733] sda: sda1
[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.410886] usbcore: registered new interface driver usb-storage
[ 3.410912] mousedev: PS/2 mouse device common for all mice
[ 3.411009] usbcore: registered new interface driver usbhid
[ 3.411010] usbhid: USB HID core driver
[ 3.411025] TCP: cubic registered
[ 3.411026] NET: Registered protocol family 17
[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.411214] devtmpfs: mounted
[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 3.446951] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.532266] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.
Starting rpcbind daemon...rpcbind: cannot create socket for udp6
rpcbind: cannot create socket for tcp6
done.
rpcbind: cannot get uid of '': Success
creating NFS state directory: done
starting statd: done

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tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate 976886 # Simulator instruction rate (inst/s)
host_mem_usage 567972 # Number of bytes of host memory used
host_op_rate 1189202 # Simulator op (including micro ops) rate (op/s)
host_seconds 146.15 # Real time elapsed on the host
host_tick_rate 19047880334 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
sim_seconds 2.783867 # Number of seconds simulated
sim_ticks 2783867052000 # Number of ticks simulated
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.clk_domain.clock 1000 # Clock period in ticks
system.cpu.Branches 36396981 # Number of branches fetched
system.cpu.committedInsts 142772879 # Number of instructions committed
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
system.cpu.dcache.overall_misses::total 814074 # number of overall misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements 819402 # number of replacements
system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
system.cpu.dcache.writebacks::total 682059 # number of writebacks
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dtb.accesses 54660704 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits 54650675 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.misses 10029 # DTB misses
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses 31534804 # DTB read accesses
system.cpu.dtb.read_hits 31526223 # DTB read hits
system.cpu.dtb.read_misses 8581 # DTB read misses
system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walks 10029 # Table walker walks requested
system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
system.cpu.dtb.write_accesses 23125900 # DTB write accesses
system.cpu.dtb.write_hits 23124452 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
system.cpu.icache.overall_hits::total 145342721 # number of overall hits
system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
system.cpu.icache.overall_misses::total 1699732 # number of overall misses
system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements 1699214 # number of replacements
system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.itb.accesses 147044108 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits 147039346 # DTB hits
system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
system.cpu.itb.inst_hits 147039346 # ITB inst hits
system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.misses 4762 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walks 4762 # Table walker walks requested
system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements 110026 # number of replacements
system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
system.cpu.l2cache.writebacks::total 101897 # number of writebacks
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
system.cpu.num_fp_insts 11484 # number of float instructions
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
system.cpu.num_func_calls 16873899 # number of times a function call or return occured
system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
system.cpu.num_int_insts 153162683 # number of integer instructions
system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
system.cpu.num_load_insts 31855884 # Number of load instructions
system.cpu.num_mem_refs 55939276 # number of memory refs
system.cpu.num_store_insts 24083392 # Number of store instructions
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 177219912 # Class of executed instruction
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.overall_misses::realview.ide 240 # number of overall misses
system.iocache.overall_misses::total 240 # number of overall misses
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.data_accesses 328176 # Number of data accesses
system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.replacements 36430 # number of replacements
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 359045 # Request fanout histogram
system.membus.snoops 0 # Total snoops (count)
system.membus.trans_dist::ReadReq 74227 # Transaction distribution
system.membus.trans_dist::ReadResp 74227 # Transaction distribution
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
system.membus.trans_dist::Writeback 138087 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.voltage_domain.voltage 1 # Voltage in Volts
---------- End Simulation Statistics ----------

208
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal Normal file
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@ -0,0 +1,208 @@
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
Kernel was built at commit id ''
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: V2P-CA15
bootconsole [earlycon0] enabled
Memory policy: Data cache writealloc
kdebugv2m: Following are test values to confirm proper working
kdebugv2m: Ranges 42000000 0
kdebugv2m: Regs 30000000 1000000
kdebugv2m: Virtual-Reg f0000000
kdebugv2m: pci node addr_cells 3
kdebugv2m: pci node size_cells 2
kdebugv2m: motherboard addr_cells 2
On node 0 totalpages: 65536
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
Normal zone: 512 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 65536 pages, LIFO batch:15
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
PID hash table entries: 1024 (order: 0, 4096 bytes)
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
.text : 0x80008000 - 0x806a942c (6790 kB)
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
.data : 0x806f4000 - 0x80732754 ( 250 kB)
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Preemptible hierarchical RCU implementation.
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
NR_IRQS:16 nr_irqs:16 16
Architected cp15 timer(s) running at 25.16MHz (phys).
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
Switching to timer-based delay loop
Console: colour dummy device 80x30
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: update cpu_power 1024
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804fee68 - 0x804fee9c
Brought up 1 CPUs
SMP: Total of 1 processors activated.
CPU: All CPU(s) started in SVC mode.
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
hw-breakpoint: CPU 0 failed to disable vector catch
Serial: AMBA PL011 UART driver
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
console [ttyAMA0] enabled
console [ttyAMA0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
pci_bus 0000:00: root bus resource [bus 00-ff]
pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
PCI: bus0: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
PCI map irq: slot 0, pin 1, devslot 0, irq: 68
PCI map irq: slot 1, pin 2, devslot 1, irq: 69
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
libata version 3.00 loaded.
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arch_sys_counter
NET: Registered protocol family 2
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 64 bytes, default 64
hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 460
io scheduler noop registered (default)
brd: module loaded
loop: module loaded
ata_piix 0000:00:01.0: version 2.13
PCI: enabling device 0000:00:01.0 (0040 -> 0041)
scsi0 : ata_piix
scsi1 : ata_piix
ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
e100: Copyright(c) 1999-2006 Intel Corporation
e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
e1000: Copyright (c) 1999-2006 Intel Corporation.
PCI: enabling device 0000:00:00.0 (0040 -> 0042)
ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
ata1.00: 1048320 sectors, multi 0: LBA
ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
igb: Copyright (c) 2007-2013 Intel Corporation.
igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
ixgbe: Copyright (c) 1999-2013 Intel Corporation.
ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
ixgb: Copyright (c) 1999-2008 Intel Corporation.
smsc911x: Driver version 2008-10-21
smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
nxp-isp1760 1b000000.usb: Scratch test failed.
nxp-isp1760 1b000000.usb: can't setup: -19
nxp-isp1760 1b000000.usb: USB bus 1 deregistered
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
ashmem: initialized
logger: created 256K log 'log_main'
logger: created 256K log 'log_events'
logger: created 256K log 'log_radio'
logger: created 256K log 'log_system'
oprofile: using timer interrupt.
TCP: cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
ALSA device list:
No soundcards found.
input: AT Raw Set 2 keyboard as /devices/smb.14/motherboard.15/iofpga.17/1c060000.kmi/serio0/input/input0
input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
VFS: Mounted root (ext2 filesystem) on device 8:1.
Freeing unused kernel memory: 292K (806aa000 - 806f3000)
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 673, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
Thu Jan 1 00:00:02 UTC 2009
S: devpts
Thu Jan 1 00:00:02 UTC 2009