ARM: Add code to extract and record VFP exceptions.
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2 changed files with 135 additions and 0 deletions
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@ -41,6 +41,8 @@
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#define __ARCH_ARM_INSTS_VFP_HH__
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#include "arch/arm/insts/misc.hh"
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#include "arch/arm/miscregs.hh"
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#include <fenv.h>
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enum VfpMicroMode {
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VfpNotAMicroop,
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@ -73,6 +75,79 @@ setVfpMicroFlags(VfpMicroMode mode, T &flags)
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}
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}
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enum FeExceptionBit
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{
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FeDivByZero = FE_DIVBYZERO,
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FeInexact = FE_INEXACT,
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FeInvalid = FE_INVALID,
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FeOverflow = FE_OVERFLOW,
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FeUnderflow = FE_UNDERFLOW,
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FeAllExceptions = FE_ALL_EXCEPT
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};
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enum FeRoundingMode
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{
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FeRoundDown = FE_DOWNWARD,
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FeRoundNearest = FE_TONEAREST,
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FeRoundZero = FE_TOWARDZERO,
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FeRoundUpward = FE_UPWARD
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};
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enum VfpRoundingMode
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{
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VfpRoundNearest = 0,
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VfpRoundUpward = 1,
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VfpRoundDown = 2,
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VfpRoundZero = 3
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};
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typedef int VfpSavedState;
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static inline VfpSavedState
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prepVfpFpscr(FPSCR fpscr)
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{
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int roundingMode = fegetround();
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feclearexcept(FeAllExceptions);
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switch (fpscr.rMode) {
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case VfpRoundNearest:
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fesetround(FeRoundNearest);
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break;
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case VfpRoundUpward:
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fesetround(FeRoundUpward);
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break;
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case VfpRoundDown:
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fesetround(FeRoundDown);
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break;
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case VfpRoundZero:
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fesetround(FeRoundZero);
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break;
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}
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return roundingMode;
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}
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static inline FPSCR
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setVfpFpscr(FPSCR fpscr, VfpSavedState state)
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{
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int exceptions = fetestexcept(FeAllExceptions);
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if (exceptions & FeInvalid) {
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fpscr.ioc = 1;
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}
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if (exceptions & FeDivByZero) {
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fpscr.dzc = 1;
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}
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if (exceptions & FeOverflow) {
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fpscr.ofc = 1;
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}
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if (exceptions & FeUnderflow) {
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fpscr.ufc = 1;
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}
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if (exceptions & FeInexact) {
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fpscr.ixc = 1;
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}
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fesetround(state);
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return fpscr;
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}
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class VfpMacroOp : public PredMacroOp
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{
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public:
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@ -376,7 +376,9 @@ let {{
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exec_output += PredOpExecute.subst(vmov2Core2RegIop);
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vmulSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1 * FpOp2;
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Fpscr = setVfpFpscr(Fpscr, state);
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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FpDest = NAN;
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}
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@ -392,7 +394,9 @@ let {{
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = cOp1.fp * cOp2.fp;
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Fpscr = setVfpFpscr(Fpscr, state);
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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cDest.fp = NAN;
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@ -456,7 +460,9 @@ let {{
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exec_output += PredOpExecute.subst(vabsDIop);
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vaddSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1 + FpOp2;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
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{ "code": vaddSCode,
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@ -469,7 +475,9 @@ let {{
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = cOp1.fp + cOp2.fp;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -481,7 +489,9 @@ let {{
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exec_output += PredOpExecute.subst(vaddDIop);
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vsubSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1 - FpOp2;
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Fpscr = setVfpFpscr(Fpscr, state)
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'''
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vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
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{ "code": vsubSCode,
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@ -494,7 +504,9 @@ let {{
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = cOp1.fp - cOp2.fp;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -506,7 +518,9 @@ let {{
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exec_output += PredOpExecute.subst(vsubDIop);
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vdivSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1 / FpOp2;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
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{ "code": vdivSCode,
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@ -519,7 +533,9 @@ let {{
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = cOp1.fp / cOp2.fp;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -531,7 +547,9 @@ let {{
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exec_output += PredOpExecute.subst(vdivDIop);
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vsqrtSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = sqrtf(FpOp1);
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Fpscr = setVfpFpscr(Fpscr, state);
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if (FpOp1 < 0) {
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FpDest = NAN;
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}
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@ -546,7 +564,9 @@ let {{
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vsqrtDCode = '''
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IntDoubleUnion cOp1, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = sqrt(cOp1.fp);
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Fpscr = setVfpFpscr(Fpscr, state);
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if (cOp1.fp < 0) {
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cDest.fp = NAN;
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}
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@ -561,11 +581,13 @@ let {{
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exec_output += PredOpExecute.subst(vsqrtDIop);
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vmlaSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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float mid = FpOp1 * FpOp2;
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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mid = NAN;
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}
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FpDest = FpDest + mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
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{ "code": vmlaSCode,
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@ -579,12 +601,14 @@ let {{
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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double mid = cOp1.fp * cOp2.fp;
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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mid = NAN;
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}
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cDest.fp = cDest.fp + mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -596,11 +620,13 @@ let {{
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exec_output += PredOpExecute.subst(vmlaDIop);
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vmlsSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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float mid = FpOp1 * FpOp2;
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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mid = NAN;
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}
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FpDest = FpDest - mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
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{ "code": vmlsSCode,
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@ -614,12 +640,14 @@ let {{
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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double mid = cOp1.fp * cOp2.fp;
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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mid = NAN;
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}
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cDest.fp = cDest.fp - mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -631,11 +659,13 @@ let {{
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exec_output += PredOpExecute.subst(vmlsDIop);
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vnmlaSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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float mid = FpOp1 * FpOp2;
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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mid = NAN;
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}
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FpDest = -FpDest - mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
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{ "code": vnmlaSCode,
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@ -649,12 +679,14 @@ let {{
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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double mid = cOp1.fp * cOp2.fp;
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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mid = NAN;
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}
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cDest.fp = -cDest.fp - mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -666,11 +698,13 @@ let {{
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exec_output += PredOpExecute.subst(vnmlaDIop);
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vnmlsSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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float mid = FpOp1 * FpOp2;
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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mid = NAN;
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}
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FpDest = -FpDest + mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
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{ "code": vnmlsSCode,
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@ -684,12 +718,14 @@ let {{
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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double mid = cOp1.fp * cOp2.fp;
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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mid = NAN;
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}
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cDest.fp = -cDest.fp + mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -701,11 +737,13 @@ let {{
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exec_output += PredOpExecute.subst(vnmlsDIop);
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vnmulSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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float mid = FpOp1 * FpOp2;
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if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
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mid = NAN;
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}
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FpDest = -mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",
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{ "code": vnmulSCode,
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@ -719,12 +757,14 @@ let {{
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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double mid = cOp1.fp * cOp2.fp;
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if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
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(isinf(cOp2.fp) && cOp1.fp == 0)) {
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mid = NAN;
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}
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cDest.fp = -mid;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -736,7 +776,9 @@ let {{
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exec_output += PredOpExecute.subst(vnmulDIop);
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vcvtUIntFpSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1.uw;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",
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{ "code": vcvtUIntFpSCode,
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@ -747,7 +789,9 @@ let {{
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vcvtUIntFpDCode = '''
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IntDoubleUnion cDest;
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = (uint64_t)FpOp1P0.uw;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -759,7 +803,9 @@ let {{
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exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
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vcvtSIntFpSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = FpOp1.sw;
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",
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{ "code": vcvtSIntFpSCode,
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@ -770,7 +816,9 @@ let {{
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vcvtSIntFpDCode = '''
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IntDoubleUnion cDest;
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = FpOp1P0.sw;
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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@ -782,7 +830,9 @@ let {{
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exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
|
||||
|
||||
vcvtFpUIntSCode = '''
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
FpDest.uw = FpOp1;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
'''
|
||||
vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
|
||||
{ "code": vcvtFpUIntSCode,
|
||||
|
@ -794,7 +844,9 @@ let {{
|
|||
vcvtFpUIntDCode = '''
|
||||
IntDoubleUnion cOp1;
|
||||
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
uint64_t result = cOp1.fp;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
|
||||
|
@ -805,7 +857,9 @@ let {{
|
|||
exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
|
||||
|
||||
vcvtFpSIntSCode = '''
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
FpDest.sw = FpOp1;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
'''
|
||||
vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
|
||||
{ "code": vcvtFpSIntSCode,
|
||||
|
@ -817,7 +871,9 @@ let {{
|
|||
vcvtFpSIntDCode = '''
|
||||
IntDoubleUnion cOp1;
|
||||
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
int64_t result = cOp1.fp;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = result;
|
||||
'''
|
||||
vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
|
||||
|
@ -829,7 +885,9 @@ let {{
|
|||
|
||||
vcvtFpSFpDCode = '''
|
||||
IntDoubleUnion cDest;
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
cDest.fp = FpOp1;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = cDest.bits;
|
||||
FpDestP1.uw = cDest.bits >> 32;
|
||||
'''
|
||||
|
@ -843,7 +901,9 @@ let {{
|
|||
vcvtFpDFpSCode = '''
|
||||
IntDoubleUnion cOp1;
|
||||
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
FpDest = cOp1.fp;
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
'''
|
||||
vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
|
||||
{ "code": vcvtFpDFpSCode,
|
||||
|
|
Loading…
Reference in a new issue