sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Have all 8 machine check registers since the kernel assumes they're there.

Browse source
This commit is contained in:
Gabe Black 2008-06-12 00:48:02 -04:00
parent a8e3001df8
commit 8688ef3fe5
2 changed files with 49 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/arch/x86/miscregs.hh
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2007 The Hewlett-Packard Development Company * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
* All rights reserved. * All rights reserved.
* *
* Redistribution and use of this software in source and binary forms, * Redistribution and use of this software in source and binary forms,
@ -183,6 +183,9 @@ namespace X86ISA
MISCREG_MC2_CTL, MISCREG_MC2_CTL,
MISCREG_MC3_CTL, MISCREG_MC3_CTL,
MISCREG_MC4_CTL, MISCREG_MC4_CTL,
MISCREG_MC5_CTL,
MISCREG_MC6_CTL,
MISCREG_MC7_CTL,
MISCREG_MC_STATUS_BASE, MISCREG_MC_STATUS_BASE,
MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
@ -190,6 +193,9 @@ namespace X86ISA
MISCREG_MC2_STATUS, MISCREG_MC2_STATUS,
MISCREG_MC3_STATUS, MISCREG_MC3_STATUS,
MISCREG_MC4_STATUS, MISCREG_MC4_STATUS,
MISCREG_MC5_STATUS,
MISCREG_MC6_STATUS,
MISCREG_MC7_STATUS,
MISCREG_MC_ADDR_BASE, MISCREG_MC_ADDR_BASE,
MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
@ -197,6 +203,9 @@ namespace X86ISA
MISCREG_MC2_ADDR, MISCREG_MC2_ADDR,
MISCREG_MC3_ADDR, MISCREG_MC3_ADDR,
MISCREG_MC4_ADDR, MISCREG_MC4_ADDR,
MISCREG_MC5_ADDR,
MISCREG_MC6_ADDR,
MISCREG_MC7_ADDR,
MISCREG_MC_MISC_BASE, MISCREG_MC_MISC_BASE,
MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
@ -204,6 +213,9 @@ namespace X86ISA
MISCREG_MC2_MISC, MISCREG_MC2_MISC,
MISCREG_MC3_MISC, MISCREG_MC3_MISC,
MISCREG_MC4_MISC, MISCREG_MC4_MISC,
MISCREG_MC5_MISC,
MISCREG_MC6_MISC,
MISCREG_MC7_MISC,
// Extended feature enable register // Extended feature enable register
MISCREG_EFER, MISCREG_EFER,

36
src/arch/x86/tlb.cc
View file

@ -358,6 +358,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
case 0x410: case 0x410:
regNum = MISCREG_MC4_CTL; regNum = MISCREG_MC4_CTL;
break; break;
case 0x414:
regNum = MISCREG_MC5_CTL;
break;
case 0x418:
regNum = MISCREG_MC6_CTL;
break;
case 0x41C:
regNum = MISCREG_MC7_CTL;
break;
case 0x401: case 0x401:
regNum = MISCREG_MC0_STATUS; regNum = MISCREG_MC0_STATUS;
break; break;
@ -373,6 +382,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
case 0x411: case 0x411:
regNum = MISCREG_MC4_STATUS; regNum = MISCREG_MC4_STATUS;
break; break;
case 0x415:
regNum = MISCREG_MC5_STATUS;
break;
case 0x419:
regNum = MISCREG_MC6_STATUS;
break;
case 0x41D:
regNum = MISCREG_MC7_STATUS;
break;
case 0x402: case 0x402:
regNum = MISCREG_MC0_ADDR; regNum = MISCREG_MC0_ADDR;
break; break;
@ -388,6 +406,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
case 0x412: case 0x412:
regNum = MISCREG_MC4_ADDR; regNum = MISCREG_MC4_ADDR;
break; break;
case 0x416:
regNum = MISCREG_MC5_ADDR;
break;
case 0x41A:
regNum = MISCREG_MC6_ADDR;
break;
case 0x41E:
regNum = MISCREG_MC7_ADDR;
break;
case 0x403: case 0x403:
regNum = MISCREG_MC0_MISC; regNum = MISCREG_MC0_MISC;
break; break;
@ -403,6 +430,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
case 0x413: case 0x413:
regNum = MISCREG_MC4_MISC; regNum = MISCREG_MC4_MISC;
break; break;
case 0x417:
regNum = MISCREG_MC5_MISC;
break;
case 0x41B:
regNum = MISCREG_MC6_MISC;
break;
case 0x41F:
regNum = MISCREG_MC7_MISC;
break;
case 0xC0000080: case 0xC0000080:
regNum = MISCREG_EFER; regNum = MISCREG_EFER;
break; break;