Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 8b5536f276527adcc27e11e790262232aeb61b13
This commit is contained in:
commit
862825f997
4 changed files with 68 additions and 14 deletions
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@ -78,6 +78,16 @@ Bus::recvTiming(Packet *pkt)
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pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
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pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
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short dest = pkt->getDest();
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short dest = pkt->getDest();
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//if (pkt->isRequest() && curTick < tickAddrLastUsed ||
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// (pkt->isResponse() || pkt->hasData()) && curTick < tickDataLastUsed) {
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//We're going to need resources that have already been committed
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//Send this guy to the back of the line
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//We don't need to worry about scheduling an event to deal with when the
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//bus is freed because that's handled when tick*LastUsed is incremented.
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// retryList.push_back(interfaces[pkt->getSrc()]);
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// return false;
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//}
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if (dest == Packet::Broadcast) {
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if (dest == Packet::Broadcast) {
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if ( timingSnoopPhase1(pkt) )
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if ( timingSnoopPhase1(pkt) )
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{
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{
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@ -95,8 +105,29 @@ Bus::recvTiming(Packet *pkt)
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assert(dest != pkt->getSrc()); // catch infinite loops
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assert(dest != pkt->getSrc()); // catch infinite loops
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port = interfaces[dest];
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port = interfaces[dest];
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}
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}
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if (port->sendTiming(pkt)) {
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if (port->sendTiming(pkt)) {
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// packet was successfully sent, just return true.
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// Packet was successfully sent.
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// Figure out what resources were used, and then return true.
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//if (pkt->isRequest()) {
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// The address bus will be used for one cycle
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// while (tickAddrLastUsed <= curTick)
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// tickAddrLastUsed += clock;
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//}
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//if (pkt->isResponse() || pkt->hasData()) {
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// Use up the data bus for at least one bus cycle
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// while (tickDataLastUsed <= curTick)
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// tickDataLastUsed += clock;
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// Use up the data bus for however many cycles remain
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// if (pkt->hasData()) {
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// int dataSize = pkt->getSize();
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// for (int transmitted = width; transmitted < dataSize;
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// transmitted += width) {
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// tickDataLastUsed += clock;
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// }
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// }
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//}
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return true;
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return true;
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}
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}
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@ -380,16 +411,20 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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Param<int> bus_id;
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Param<int> clock;
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Param<int> width;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "a globally unique bus id")
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INIT_PARAM(bus_id, "a globally unique bus id"),
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INIT_PARAM(clock, "bus clock speed"),
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INIT_PARAM(width, "width of the bus (bits)")
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END_INIT_SIM_OBJECT_PARAMS(Bus)
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END_INIT_SIM_OBJECT_PARAMS(Bus)
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CREATE_SIM_OBJECT(Bus)
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CREATE_SIM_OBJECT(Bus)
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{
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{
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return new Bus(getInstanceName(), bus_id);
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return new Bus(getInstanceName(), bus_id, clock, width);
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}
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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REGISTER_SIM_OBJECT("Bus", Bus)
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@ -51,6 +51,14 @@ class Bus : public MemObject
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{
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{
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/** a globally unique id for this bus. */
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/** a globally unique id for this bus. */
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int busId;
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int busId;
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/** the clock speed for the bus */
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int clock;
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/** the width of the bus in bits */
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int width;
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/** the last tick the address bus was used */
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Tick tickAddrLastUsed;
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/** the last tick the data bus was used */
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Tick tickDataLastUsed;
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static const int defaultId = -1;
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static const int defaultId = -1;
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@ -199,8 +207,12 @@ class Bus : public MemObject
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virtual void init();
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virtual void init();
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Bus(const std::string &n, int bus_id)
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Bus(const std::string &n, int bus_id, int _clock, int _width)
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: MemObject(n), busId(bus_id), defaultPort(NULL) {}
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: MemObject(n), busId(bus_id), clock(_clock), width(_width),
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tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL)
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{
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assert(width);
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}
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};
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};
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@ -174,7 +174,8 @@ class Packet
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IsResponse = 1 << 5,
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IsResponse = 1 << 5,
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NeedsResponse = 1 << 6,
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NeedsResponse = 1 << 6,
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IsSWPrefetch = 1 << 7,
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IsSWPrefetch = 1 << 7,
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IsHWPrefetch = 1 << 8
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IsHWPrefetch = 1 << 8,
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HasData = 1 << 9
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};
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};
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public:
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public:
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@ -183,21 +184,24 @@ class Packet
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{
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{
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InvalidCmd = 0,
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InvalidCmd = 0,
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ReadReq = IsRead | IsRequest | NeedsResponse,
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ReadReq = IsRead | IsRequest | NeedsResponse,
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WriteReq = IsWrite | IsRequest | NeedsResponse,
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WriteReq = IsWrite | IsRequest | NeedsResponse,// | HasData,
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WriteReqNoAck = IsWrite | IsRequest,
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WriteReqNoAck = IsWrite | IsRequest,// | HasData,
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ReadResp = IsRead | IsResponse | NeedsResponse,
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ReadResp = IsRead | IsResponse | NeedsResponse,// | HasData,
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WriteResp = IsWrite | IsResponse | NeedsResponse,
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WriteResp = IsWrite | IsResponse | NeedsResponse,
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Writeback = IsWrite | IsRequest,
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Writeback = IsWrite | IsRequest,// | HasData,
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SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse,
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SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse,
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HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse,
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HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse,
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SoftPFResp = IsRead | IsResponse | IsSWPrefetch | NeedsResponse,
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SoftPFResp = IsRead | IsResponse | IsSWPrefetch
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HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
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| NeedsResponse,// | HasData,
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HardPFResp = IsRead | IsResponse | IsHWPrefetch
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| NeedsResponse,// | HasData,
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InvalidateReq = IsInvalidate | IsRequest,
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InvalidateReq = IsInvalidate | IsRequest,
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WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
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WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,// | HasData,
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UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
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UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
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UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
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UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
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ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
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ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
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ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
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ReadExResp = IsRead | IsInvalidate | IsResponse
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| NeedsResponse,// | HasData
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};
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};
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/** Return the string name of the cmd field (for debugging and
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/** Return the string name of the cmd field (for debugging and
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@ -219,6 +223,7 @@ class Packet
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bool isResponse() { return (cmd & IsResponse) != 0; }
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bool isResponse() { return (cmd & IsResponse) != 0; }
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bool needsResponse() { return (cmd & NeedsResponse) != 0; }
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bool needsResponse() { return (cmd & NeedsResponse) != 0; }
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bool isInvalidate() { return (cmd & IsInvalidate) != 0; }
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bool isInvalidate() { return (cmd & IsInvalidate) != 0; }
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bool hasData() { return (cmd & HasData) != 0; }
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bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; }
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bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; }
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bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
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bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
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@ -6,3 +6,5 @@ class Bus(MemObject):
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port = VectorPort("vector port for connecting devices")
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port = VectorPort("vector port for connecting devices")
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default = Port("Default port for requests that aren't handeled by a device.")
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default = Port("Default port for requests that aren't handeled by a device.")
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bus_id = Param.Int(0, "blah")
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bus_id = Param.Int(0, "blah")
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clock = Param.Clock("1GHz", "bus clock speed")
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width = Param.Int(64, "bus width (bits)")
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