config: fixed ruby dma device connections
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e983ef9e8c
commit
8572d8fd91
5 changed files with 10 additions and 12 deletions
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@ -124,9 +124,10 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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self.tsunami.ethernet.pio = self.piobus.port
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self.tsunami.ethernet.pio = self.piobus.port
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#
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#
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# store the dma devices for later connection to dma ruby ports
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_devices to avoid the SimObjectVector check.
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#
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#
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self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
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self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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read_only = True))
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@ -115,7 +115,7 @@ system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
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system.ruby = Ruby.create_system(options,
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system.ruby = Ruby.create_system(options,
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system,
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system,
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system.piobus,
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system.piobus,
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system.dma_devices)
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system._dma_devices)
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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@ -151,12 +151,11 @@ def create_system(options, system, piobus, dma_devices):
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dma_cntrl = DMA_Controller(version = i,
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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dma_sequencer = dma_seq)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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if dma_device.type == 'MemTest':
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system.dma_cntrl.dma_sequencer.port = dma_device.test
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
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else:
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else:
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system.dma_cntrl.dma_sequencer.port = dma_device.dma
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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all_cntrls = l1_cntrl_nodes + \
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@ -152,10 +152,9 @@ def create_system(options, system, piobus, dma_devices):
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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if dma_device.type == 'MemTest':
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system.dma_cntrl.dma_sequencer.port = dma_device.test
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
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else:
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else:
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system.dma_cntrl.dma_sequencer.port = dma_device.dma
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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all_cntrls = l1_cntrl_nodes + \
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@ -178,10 +178,9 @@ def create_system(options, system, piobus, dma_devices):
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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if dma_device.type == 'MemTest':
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system.dma_cntrl.dma_sequencer.port = dma_device.test
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
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else:
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else:
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system.dma_cntrl.dma_sequencer.port = dma_device.dma
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exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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all_cntrls = l1_cntrl_nodes + \
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