X86: Add in some support for the tsc register.

src/arch/x86/isa/decoder/two_byte_opcodes.isa

@@ -317,7 +317,7 @@
             }
             0x06: decode OPCODE_OP_BOTTOM3 {
                 0x0: Inst::WRMSR();
-                0x1: rdtsc();
+                0x1: Inst::RDTSC();
                 0x2: Inst::RDMSR();
                 0x3: rdpmc();
                 0x4: sysenter();

src/arch/x86/isa/insts/system/msrs.py

@@ -99,4 +99,12 @@ def macroop WRMSR
     or t2, t2, t3, dataSize=8
     st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
 };
+
+def macroop RDTSC
+{
+    rdtsc t1
+    mov rax, rax, t1, dataSize=4
+    srli t1, t1, 32, dataSize=8
+    mov rdx, rdx, t1, dataSize=4
+};
 '''

src/arch/x86/isa/microops/regop.isa

@@ -1,4 +1,4 @@
-// Copyright (c) 2007 The Hewlett-Packard Development Company
+// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
 // All rights reserved.
 //
 // Redistribution and use of this software in source and binary forms,
@@ -1018,6 +1018,16 @@ let {{
 
         '''
 
+    class Wrtsc(WrRegOp):
+        code = '''
+            TscOp = psrc1;
+        '''
+
+    class Rdtsc(RdRegOp):
+        code = '''
+            DestReg = TscOp;
+        '''
+
     class Wrdl(RegOp):
         code = '''
             SegDescriptor desc = SrcReg1;

src/arch/x86/isa/operands.isa

@@ -26,7 +26,7 @@
 //
 // Authors: Gabe Black
 
-// Copyright (c) 2007 The Hewlett-Packard Development Company
+// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
 // All rights reserved.
 //
 // Redistribution and use of this software in source and binary forms,
@@ -146,5 +146,6 @@ def operands {{
         'GDTRBase':      ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
         'GDTRLimit':     ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
         'CSBase':        ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
+        'TscOp':         ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 208),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
 }};

src/arch/x86/miscregfile.cc

@@ -87,6 +87,7 @@
 
 #include "arch/x86/miscregfile.hh"
 #include "arch/x86/tlb.hh"
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "sim/serialize.hh"
 
@@ -178,6 +179,10 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
             break;
         }
     }
+    switch (miscReg) {
+      case MISCREG_TSC:
+        return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
+    }
     return readRegNoEffect(miscReg);
 }
 
@@ -377,6 +382,9 @@ void MiscRegFile::setReg(int miscReg,
                         MISCREG_SEG_BASE_BASE)] = val;
         }
         break;
+      case MISCREG_TSC:
+        regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
+        return;
     }
     setRegNoEffect(miscReg, newVal);
 }