X86: Add in some support for the tsc register.
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@ -317,7 +317,7 @@
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}
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}
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x0: Inst::WRMSR();
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0x0: Inst::WRMSR();
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0x1: rdtsc();
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0x1: Inst::RDTSC();
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0x2: Inst::RDMSR();
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0x2: Inst::RDMSR();
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0x3: rdpmc();
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0x3: rdpmc();
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0x4: sysenter();
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0x4: sysenter();
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@ -99,4 +99,12 @@ def macroop WRMSR
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or t2, t2, t3, dataSize=8
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or t2, t2, t3, dataSize=8
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st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
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st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
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};
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};
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def macroop RDTSC
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{
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rdtsc t1
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mov rax, rax, t1, dataSize=4
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srli t1, t1, 32, dataSize=8
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mov rdx, rdx, t1, dataSize=4
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};
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'''
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'''
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@ -1,4 +1,4 @@
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// Copyright (c) 2007 The Hewlett-Packard Development Company
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use of this software in source and binary forms,
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// Redistribution and use of this software in source and binary forms,
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@ -1018,6 +1018,16 @@ let {{
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'''
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'''
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class Wrtsc(WrRegOp):
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code = '''
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TscOp = psrc1;
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'''
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class Rdtsc(RdRegOp):
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code = '''
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DestReg = TscOp;
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'''
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class Wrdl(RegOp):
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class Wrdl(RegOp):
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code = '''
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code = '''
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SegDescriptor desc = SrcReg1;
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SegDescriptor desc = SrcReg1;
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@ -26,7 +26,7 @@
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//
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//
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// Authors: Gabe Black
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// Authors: Gabe Black
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// Copyright (c) 2007 The Hewlett-Packard Development Company
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use of this software in source and binary forms,
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// Redistribution and use of this software in source and binary forms,
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@ -146,5 +146,6 @@ def operands {{
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'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
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'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
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'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
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'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
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'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 208),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
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}};
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}};
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@ -87,6 +87,7 @@
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#include "arch/x86/miscregfile.hh"
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#include "arch/x86/miscregfile.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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#include "sim/serialize.hh"
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#include "sim/serialize.hh"
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@ -178,6 +179,10 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
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break;
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break;
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}
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}
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}
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}
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switch (miscReg) {
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case MISCREG_TSC:
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return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
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}
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return readRegNoEffect(miscReg);
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return readRegNoEffect(miscReg);
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}
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}
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@ -377,6 +382,9 @@ void MiscRegFile::setReg(int miscReg,
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MISCREG_SEG_BASE_BASE)] = val;
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MISCREG_SEG_BASE_BASE)] = val;
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}
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}
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break;
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break;
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case MISCREG_TSC:
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regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
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return;
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}
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}
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setRegNoEffect(miscReg, newVal);
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setRegNoEffect(miscReg, newVal);
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}
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}
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