config: Refactor RealviewEMM to fit into new config system
This eliminates some default devices and adds in helper functions to connect the devices defined here to associate with the proper clock domains.
This commit is contained in:
Geoffrey Blake
parent
a217eba078
commit
845e199934
2 changed files with 152 additions and 20 deletions
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@ -221,6 +221,9 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None,
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self.cf0 = CowIdeDisk(driveID='master')
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self.cf0.childImage(mdesc.disk())
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# Attach any PCI devices this platform supports
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self.realview.attachPciDevices()
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# default to an IDE controller rather than a CF one
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# assuming we've got one; EMM64 is an exception for the moment
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if machine_type != "VExpress_EMM64":
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@ -1,4 +1,4 @@
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# Copyright (c) 2009-2013 ARM Limited
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# Copyright (c) 2009-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -44,7 +44,7 @@ from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
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from Pci import PciConfigAll
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from Ethernet import NSGigE, IGbE_e1000, IGbE_igb
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from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
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from Ide import *
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from Platform import Platform
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from Terminal import Terminal
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@ -184,6 +184,18 @@ class RealView(Platform):
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mem_start_addr = Param.Addr(0, "Start address of main memory")
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max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform")
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def attachPciDevices(self):
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pass
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def enableMSIX(self):
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pass
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def onChipIOClkDomain(self, clkdomain):
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pass
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def offChipIOClkDomain(self, clkdomain):
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pass
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
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conf_table_reported = False)
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@ -250,6 +262,14 @@ class RealViewPBX(RealView):
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self.flash_fake.pio_addr + \
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self.flash_fake.pio_size - 1)]
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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self.a9scu.clkdomain = clkdomain
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self.local_cpu_timer.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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@ -282,12 +302,40 @@ class RealViewPBX(RealView):
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self.rtc.pio = bus.master
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self.flash_fake.pio = bus.master
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.cf_ctrl.clk_domain = clkdomain
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self.dmac_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.smc_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.gpio0_fake.clk_domain = clkdomain
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self.gpio1_fake.clk_domain = clkdomain
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self.gpio2_fake.clk_domain = clkdomain
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self.ssp_fake.clk_domain = clkdomain
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self.sci_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.flash_fake.clk_domain = clkdomain
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# Reference for memory map and interrupt number
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# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
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# Chapter 4: Programmer's Reference
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class RealViewEB(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000)
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realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
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gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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@ -328,6 +376,12 @@ class RealViewEB(RealView):
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self.gic.cpu_addr - 1),
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AddrRange(self.flash_fake.pio_addr, Addr.max)]
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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@ -358,12 +412,41 @@ class RealViewEB(RealView):
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self.flash_fake.pio = bus.master
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self.smcreg_fake.pio = bus.master
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.dmac_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.smc_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.gpio0_fake.clk_domain = clkdomain
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self.gpio1_fake.clk_domain = clkdomain
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self.gpio2_fake.clk_domain = clkdomain
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self.ssp_fake.clk_domain = clkdomain
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self.sci_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.flash_fake.clk_domain = clkdomain
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self.smcreg_fake.clk_domain = clkdomain
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class VExpress_EMM(RealView):
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mem_start_addr = '2GB'
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max_mem_size = '2GB'
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pci_cfg_base = 0x30000000
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uart = Pl011(pio_addr=0x1c090000, int_num=37)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \
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idreg=0x02250000, pio_addr=0x1C010000)
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gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
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local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
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generic_timer = GenericTimer(int_num=29)
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@ -381,13 +464,6 @@ class VExpress_EMM(RealView):
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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pciconfig = PciConfigAll(size='256MB')
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ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
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InterruptLine=1, InterruptPin=1)
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ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
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InterruptLine=2, InterruptPin=2)
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vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
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conf_table_reported = False)
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rtc = PL031(pio_addr=0x1C170000, int_num=36)
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@ -403,6 +479,18 @@ class VExpress_EMM(RealView):
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usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
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mmc_fake = AmbaFake(pio_addr=0x1c050000)
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# Attach any PCI devices that are supported
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def attachPciDevices(self):
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self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
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InterruptLine=1, InterruptPin=1)
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self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
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InterruptLine=2, InterruptPin=2)
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def enableMSIX(self):
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self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
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self.gicv2m = Gicv2m()
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self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange('64MB'),
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conf_table_reported = False)
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@ -417,6 +505,8 @@ class VExpress_EMM(RealView):
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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if hasattr(self, "gicv2m"):
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self.gicv2m.pio = bus.master
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self.hdlcd.dma = bus.slave
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, a9scu)
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@ -429,9 +519,17 @@ class VExpress_EMM(RealView):
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self.vgic.pio = bus.master
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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if hasattr(self, "gicv2m"):
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self.gicv2m.clk_domain = clkdomain
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self.hdlcd.clk_domain = clkdomain
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self.vgic.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Done here
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# as the specified bus to connect to may not always be fixed.
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def attachIO(self, bus):
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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@ -448,12 +546,6 @@ class VExpress_EMM(RealView):
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self.rtc.pio = bus.master
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bus.use_default_range = True
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self.vram.port = bus.master
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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self.ethernet.pio = bus.master
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self.ethernet.config = bus.master
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self.ethernet.dma = bus.slave
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self.pciconfig.pio = bus.default
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self.l2x0_fake.pio = bus.master
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@ -467,6 +559,43 @@ class VExpress_EMM(RealView):
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self.usb_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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# Try to attach the I/O if it exists
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try:
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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self.ethernet.pio = bus.master
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self.ethernet.config = bus.master
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self.ethernet.dma = bus.slave
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except:
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pass
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.cf_ctrl.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.vram.clk_domain = clkdomain
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self.pciconfig.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.lan_fake.clk_domain = clkdomain
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self.usb_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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class VExpress_EMM64(VExpress_EMM):
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
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