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Add comment to elaborate on store-conditional result code (and remove

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stale reference to machine.def).

arch/alpha/isa_desc:
    Add comment describing store-conditional result code
cpu/exec_context.hh:
    update comments

--HG--
extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55
This commit is contained in:
Steve Reinhardt 2003-10-18 21:21:14 -07:00
parent 1bebc1ab2f
commit 83d32482dc
2 changed files with 14 additions and 7 deletions
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8
arch/alpha/isa_desc
View file

@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() {
0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }}, 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }},
{{ {{
uint64_t tmp = Mem_write_result; uint64_t tmp = Mem_write_result;
// see stq_c
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
}}, LOCKED); }}, LOCKED);
0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }}, 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }},
{{ {{
uint64_t tmp = Mem_write_result; uint64_t tmp = Mem_write_result;
// If the write operation returns 0 or 1, then
// this was a conventional store conditional,
// and the value indicates the success/failure
// of the operation. If another value is
// returned, then this was a Turbolaser
// mailbox access, and we don't update the
// result register at all.
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
}}, LOCKED); }}, LOCKED);
} }

13
cpu/exec_context.hh
View file

@ -218,7 +218,7 @@ class ExecContext
cregs = &req->xc->regs.miscRegs; cregs = &req->xc->regs.miscRegs;
if (req->flags & UNCACHEABLE) { if (req->flags & UNCACHEABLE) {
// Don't update result register (see machine.def) // Don't update result register (see stq_c in isa_desc)
req->result = 2; req->result = 2;
req->xc->storeCondFailures = 0;//Needed? [RGD] req->xc->storeCondFailures = 0;//Needed? [RGD]
} else { } else {
@ -239,12 +239,11 @@ class ExecContext
} }
} }
// Need to clear any locked flags on other proccessors for this // Need to clear any locked flags on other proccessors for
// address // this address. Only do this for succsful Store Conditionals
// Only do this for succsful Store Conditionals and all other // and all other stores (WH64?). Unsuccessful Store
// stores (WH64?) // Conditionals would have returned above, and wouldn't fall
// Unsuccesful Store Conditionals would have returned above, // through.
// and wouldn't fall through
for (int i = 0; i < system->xcvec.size(); i++){ for (int i = 0; i < system->xcvec.size(); i++){
cregs = &system->xcvec[i]->regs.miscRegs; cregs = &system->xcvec[i]->regs.miscRegs;
if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {