CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.
--HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
This commit is contained in:
parent
6010f350a4
commit
8351660273
5 changed files with 17 additions and 9 deletions
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@ -159,9 +159,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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icachePort.snoopRangeSent = false;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
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ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
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}
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}
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@ -237,6 +237,8 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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if (_status != Running) {
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if (_status != Running) {
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_status = Idle;
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_status = Idle;
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}
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}
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assert(threadContexts.size() == 1);
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cpuId = tc->readCpuId();
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}
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}
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@ -91,6 +91,8 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
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threadContexts.push_back(tc);
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threadContexts.push_back(tc);
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cpuId = tc->readCpuId();
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fetchOffset = 0;
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fetchOffset = 0;
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stayAtPC = false;
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stayAtPC = false;
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}
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}
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@ -117,6 +117,10 @@ class BaseSimpleCPU : public BaseCPU
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* objects to modify this thread's state.
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* objects to modify this thread's state.
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*/
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*/
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ThreadContext *tc;
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ThreadContext *tc;
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protected:
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int cpuId;
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public:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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Addr dbg_vtophys(Addr addr);
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@ -104,8 +104,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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}
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}
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TimingSimpleCPU::TimingSimpleCPU(Params *p)
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TimingSimpleCPU::TimingSimpleCPU(Params *p)
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: BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
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: BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
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cpu_id(p->cpu_id)
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{
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{
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_status = Idle;
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_status = Idle;
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@ -207,6 +206,8 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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if (_status != Running) {
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if (_status != Running) {
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_status = Idle;
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_status = Idle;
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}
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}
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assert(threadContexts.size() == 1);
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cpuId = tc->readCpuId();
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previousTick = curTick;
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previousTick = curTick;
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}
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}
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@ -249,7 +250,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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{
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Request *req =
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Request *req =
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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cpu_id, /* thread ID */ 0);
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cpuId, /* thread ID */ 0);
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if (traceData) {
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if (traceData) {
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traceData->setAddr(req->getVaddr());
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traceData->setAddr(req->getVaddr());
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@ -349,7 +350,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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{
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Request *req =
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Request *req =
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
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cpu_id, /* thread ID */ 0);
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cpuId, /* thread ID */ 0);
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if (traceData) {
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if (traceData) {
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traceData->setAddr(req->getVaddr());
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traceData->setAddr(req->getVaddr());
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@ -474,7 +475,7 @@ TimingSimpleCPU::fetch()
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checkForInterrupts();
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checkForInterrupts();
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Request *ifetch_req = new Request();
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Request *ifetch_req = new Request();
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ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
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ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
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Fault fault = setupFetchRequest(ifetch_req);
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Fault fault = setupFetchRequest(ifetch_req);
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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@ -168,7 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
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PacketPtr ifetch_pkt;
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PacketPtr ifetch_pkt;
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PacketPtr dcache_pkt;
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PacketPtr dcache_pkt;
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int cpu_id;
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Tick previousTick;
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Tick previousTick;
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public:
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public:
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