Move the "translate" member functions back into the base o3 class.

--HG--
extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
This commit is contained in:
Gabe Black 2007-08-13 16:01:09 -07:00
parent 9b4be65327
commit 82f78ebd39
4 changed files with 41 additions and 97 deletions

View file

@ -66,45 +66,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
/** Registers statistics. */ /** Registers statistics. */
void regStats(); void regStats();
#if FULL_SYSTEM
/** Translates instruction requestion. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return this->itb->translate(req, thread->getTC());
}
/** Translates data read request. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), false);
}
/** Translates data write request. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), true);
}
#else
/** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
#endif
/** Reads a miscellaneous register. */ /** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);

View file

@ -94,9 +94,9 @@ class FullO3CPU : public BaseO3CPU
public: public:
// Typedefs from the Impl here. // Typedefs from the Impl here.
typedef typename Impl::CPUPol CPUPolicy; typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::O3CPU O3CPU; typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::Params Params;
typedef O3ThreadState<Impl> Thread; typedef O3ThreadState<Impl> Thread;
@ -265,6 +265,46 @@ class FullO3CPU : public BaseO3CPU
/** Registers statistics. */ /** Registers statistics. */
void fullCPURegStats(); void fullCPURegStats();
#if FULL_SYSTEM
/** Translates instruction requestion. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return this->itb->translate(req, thread->getTC());
}
/** Translates data read request. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), false);
}
/** Translates data write request. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), true);
}
#else
/** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
#endif
/** Returns a specific port. */ /** Returns a specific port. */
Port *getPort(const std::string &if_name, int idx); Port *getPort(const std::string &if_name, int idx);

View file

@ -68,24 +68,6 @@ class MipsO3CPU : public FullO3CPU<Impl>
/** Registers statistics. */ /** Registers statistics. */
void regStats(); void regStats();
/** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Reads a miscellaneous register. */ /** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);

View file

@ -66,45 +66,6 @@ class SparcO3CPU : public FullO3CPU<Impl>
/** Registers statistics. */ /** Registers statistics. */
void regStats(); void regStats();
#if FULL_SYSTEM
/** Translates instruction requestion. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return this->itb->translate(req, thread->getTC());
}
/** Translates data read request. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), false);
}
/** Translates data write request. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return this->dtb->translate(req, thread->getTC(), true);
}
#else
/** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
#endif
/** Reads a miscellaneous register. */ /** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);