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alpha: Clean up namespace usage.

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This commit is contained in:
Nathan Binkert 2008-09-27 21:03:47 -07:00
parent 8ea5176b7f
commit 82f5723c7a
23 changed files with 300 additions and 297 deletions
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367
src/arch/alpha/ev5.cc
View file

@ -44,7 +44,7 @@
#include "sim/debug.hh" #include "sim/debug.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"
using namespace AlphaISA; namespace AlphaISA {
#if FULL_SYSTEM #if FULL_SYSTEM
@ -53,14 +53,14 @@ using namespace AlphaISA;
// Machine dependent functions // Machine dependent functions
// //
void void
AlphaISA::initCPU(ThreadContext *tc, int cpuId) initCPU(ThreadContext *tc, int cpuId)
{ {
initIPRs(tc, cpuId); initIPRs(tc, cpuId);
tc->setIntReg(16, cpuId); tc->setIntReg(16, cpuId);
tc->setIntReg(0, cpuId); tc->setIntReg(0, cpuId);
AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; AlphaFault *reset = new ResetFault;
tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst)); tc->setNextPC(tc->readPC() + sizeof(MachInst));
@ -71,7 +71,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
template <class CPU> template <class CPU>
void void
AlphaISA::processInterrupts(CPU *cpu) processInterrupts(CPU *cpu)
{ {
//Check if there are any outstanding interrupts //Check if there are any outstanding interrupts
//Handle the interrupts //Handle the interrupts
@ -117,7 +117,7 @@ AlphaISA::processInterrupts(CPU *cpu)
template <class CPU> template <class CPU>
void void
AlphaISA::zeroRegisters(CPU *cpu) zeroRegisters(CPU *cpu)
{ {
// Insure ISA semantics // Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the // (no longer very clean due to the change in setIntReg() in the
@ -126,33 +126,16 @@ AlphaISA::zeroRegisters(CPU *cpu)
cpu->thread->setFloatReg(ZeroReg, 0.0); cpu->thread->setFloatReg(ZeroReg, 0.0);
} }
Fault int
SimpleThread::hwrei() MiscRegFile::getInstAsid()
{ {
if (!(readPC() & 0x3)) return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
return new UnimplementedOpcodeFault;
setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
if (kernelStats)
kernelStats->hwrei();
}
// FIXME: XXX check for interrupts? XXX
return NoFault;
} }
int int
AlphaISA::MiscRegFile::getInstAsid() MiscRegFile::getDataAsid()
{ {
return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
int
AlphaISA::MiscRegFile::getDataAsid()
{
return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
} }
#endif #endif
@ -162,90 +145,90 @@ AlphaISA::MiscRegFile::getDataAsid()
// //
// //
void void
AlphaISA::initIPRs(ThreadContext *tc, int cpuId) initIPRs(ThreadContext *tc, int cpuId)
{ {
for (int i = 0; i < NumInternalProcRegs; ++i) { for (int i = 0; i < NumInternalProcRegs; ++i) {
tc->setMiscRegNoEffect(i, 0); tc->setMiscRegNoEffect(i, 0);
} }
tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase); tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6); tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
} }
AlphaISA::MiscReg MiscReg
AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) MiscRegFile::readIpr(int idx, ThreadContext *tc)
{ {
uint64_t retval = 0; // return value, default 0 uint64_t retval = 0; // return value, default 0
switch (idx) { switch (idx) {
case AlphaISA::IPR_PALtemp0: case IPR_PALtemp0:
case AlphaISA::IPR_PALtemp1: case IPR_PALtemp1:
case AlphaISA::IPR_PALtemp2: case IPR_PALtemp2:
case AlphaISA::IPR_PALtemp3: case IPR_PALtemp3:
case AlphaISA::IPR_PALtemp4: case IPR_PALtemp4:
case AlphaISA::IPR_PALtemp5: case IPR_PALtemp5:
case AlphaISA::IPR_PALtemp6: case IPR_PALtemp6:
case AlphaISA::IPR_PALtemp7: case IPR_PALtemp7:
case AlphaISA::IPR_PALtemp8: case IPR_PALtemp8:
case AlphaISA::IPR_PALtemp9: case IPR_PALtemp9:
case AlphaISA::IPR_PALtemp10: case IPR_PALtemp10:
case AlphaISA::IPR_PALtemp11: case IPR_PALtemp11:
case AlphaISA::IPR_PALtemp12: case IPR_PALtemp12:
case AlphaISA::IPR_PALtemp13: case IPR_PALtemp13:
case AlphaISA::IPR_PALtemp14: case IPR_PALtemp14:
case AlphaISA::IPR_PALtemp15: case IPR_PALtemp15:
case AlphaISA::IPR_PALtemp16: case IPR_PALtemp16:
case AlphaISA::IPR_PALtemp17: case IPR_PALtemp17:
case AlphaISA::IPR_PALtemp18: case IPR_PALtemp18:
case AlphaISA::IPR_PALtemp19: case IPR_PALtemp19:
case AlphaISA::IPR_PALtemp20: case IPR_PALtemp20:
case AlphaISA::IPR_PALtemp21: case IPR_PALtemp21:
case AlphaISA::IPR_PALtemp22: case IPR_PALtemp22:
case AlphaISA::IPR_PALtemp23: case IPR_PALtemp23:
case AlphaISA::IPR_PAL_BASE: case IPR_PAL_BASE:
case AlphaISA::IPR_IVPTBR: case IPR_IVPTBR:
case AlphaISA::IPR_DC_MODE: case IPR_DC_MODE:
case AlphaISA::IPR_MAF_MODE: case IPR_MAF_MODE:
case AlphaISA::IPR_ISR: case IPR_ISR:
case AlphaISA::IPR_EXC_ADDR: case IPR_EXC_ADDR:
case AlphaISA::IPR_IC_PERR_STAT: case IPR_IC_PERR_STAT:
case AlphaISA::IPR_DC_PERR_STAT: case IPR_DC_PERR_STAT:
case AlphaISA::IPR_MCSR: case IPR_MCSR:
case AlphaISA::IPR_ASTRR: case IPR_ASTRR:
case AlphaISA::IPR_ASTER: case IPR_ASTER:
case AlphaISA::IPR_SIRR: case IPR_SIRR:
case AlphaISA::IPR_ICSR: case IPR_ICSR:
case AlphaISA::IPR_ICM: case IPR_ICM:
case AlphaISA::IPR_DTB_CM: case IPR_DTB_CM:
case AlphaISA::IPR_IPLR: case IPR_IPLR:
case AlphaISA::IPR_INTID: case IPR_INTID:
case AlphaISA::IPR_PMCTR: case IPR_PMCTR:
// no side-effect // no side-effect
retval = ipr[idx]; retval = ipr[idx];
break; break;
case AlphaISA::IPR_CC: case IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
break; break;
case AlphaISA::IPR_VA: case IPR_VA:
retval = ipr[idx]; retval = ipr[idx];
break; break;
case AlphaISA::IPR_VA_FORM: case IPR_VA_FORM:
case AlphaISA::IPR_MM_STAT: case IPR_MM_STAT:
case AlphaISA::IPR_IFAULT_VA_FORM: case IPR_IFAULT_VA_FORM:
case AlphaISA::IPR_EXC_MASK: case IPR_EXC_MASK:
case AlphaISA::IPR_EXC_SUM: case IPR_EXC_SUM:
retval = ipr[idx]; retval = ipr[idx];
break; break;
case AlphaISA::IPR_DTB_PTE: case IPR_DTB_PTE:
{ {
AlphaISA::TlbEntry &entry TlbEntry &entry
= tc->getDTBPtr()->index(!tc->misspeculating()); = tc->getDTBPtr()->index(!tc->misspeculating());
retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
@ -259,15 +242,15 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
break; break;
// write only registers // write only registers
case AlphaISA::IPR_HWINT_CLR: case IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT: case IPR_SL_XMIT:
case AlphaISA::IPR_DC_FLUSH: case IPR_DC_FLUSH:
case AlphaISA::IPR_IC_FLUSH: case IPR_IC_FLUSH:
case AlphaISA::IPR_ALT_MODE: case IPR_ALT_MODE:
case AlphaISA::IPR_DTB_IA: case IPR_DTB_IA:
case AlphaISA::IPR_DTB_IAP: case IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA: case IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP: case IPR_ITB_IAP:
panic("Tried to read write only register %d\n", idx); panic("Tried to read write only register %d\n", idx);
break; break;
@ -286,7 +269,7 @@ int break_ipl = -1;
#endif #endif
void void
AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
{ {
uint64_t old; uint64_t old;
@ -294,52 +277,52 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
return; return;
switch (idx) { switch (idx) {
case AlphaISA::IPR_PALtemp0: case IPR_PALtemp0:
case AlphaISA::IPR_PALtemp1: case IPR_PALtemp1:
case AlphaISA::IPR_PALtemp2: case IPR_PALtemp2:
case AlphaISA::IPR_PALtemp3: case IPR_PALtemp3:
case AlphaISA::IPR_PALtemp4: case IPR_PALtemp4:
case AlphaISA::IPR_PALtemp5: case IPR_PALtemp5:
case AlphaISA::IPR_PALtemp6: case IPR_PALtemp6:
case AlphaISA::IPR_PALtemp7: case IPR_PALtemp7:
case AlphaISA::IPR_PALtemp8: case IPR_PALtemp8:
case AlphaISA::IPR_PALtemp9: case IPR_PALtemp9:
case AlphaISA::IPR_PALtemp10: case IPR_PALtemp10:
case AlphaISA::IPR_PALtemp11: case IPR_PALtemp11:
case AlphaISA::IPR_PALtemp12: case IPR_PALtemp12:
case AlphaISA::IPR_PALtemp13: case IPR_PALtemp13:
case AlphaISA::IPR_PALtemp14: case IPR_PALtemp14:
case AlphaISA::IPR_PALtemp15: case IPR_PALtemp15:
case AlphaISA::IPR_PALtemp16: case IPR_PALtemp16:
case AlphaISA::IPR_PALtemp17: case IPR_PALtemp17:
case AlphaISA::IPR_PALtemp18: case IPR_PALtemp18:
case AlphaISA::IPR_PALtemp19: case IPR_PALtemp19:
case AlphaISA::IPR_PALtemp20: case IPR_PALtemp20:
case AlphaISA::IPR_PALtemp21: case IPR_PALtemp21:
case AlphaISA::IPR_PALtemp22: case IPR_PALtemp22:
case AlphaISA::IPR_PAL_BASE: case IPR_PAL_BASE:
case AlphaISA::IPR_IC_PERR_STAT: case IPR_IC_PERR_STAT:
case AlphaISA::IPR_DC_PERR_STAT: case IPR_DC_PERR_STAT:
case AlphaISA::IPR_PMCTR: case IPR_PMCTR:
// write entire quad w/ no side-effect // write entire quad w/ no side-effect
ipr[idx] = val; ipr[idx] = val;
break; break;
case AlphaISA::IPR_CC_CTL: case IPR_CC_CTL:
// This IPR resets the cycle counter. We assume this only // This IPR resets the cycle counter. We assume this only
// happens once... let's verify that. // happens once... let's verify that.
assert(ipr[idx] == 0); assert(ipr[idx] == 0);
ipr[idx] = 1; ipr[idx] = 1;
break; break;
case AlphaISA::IPR_CC: case IPR_CC:
// This IPR only writes the upper 64 bits. It's ok to write // This IPR only writes the upper 64 bits. It's ok to write
// all 64 here since we mask out the lower 32 in rpcc (see // all 64 here since we mask out the lower 32 in rpcc (see
// isa_desc). // isa_desc).
ipr[idx] = val; ipr[idx] = val;
break; break;
case AlphaISA::IPR_PALtemp23: case IPR_PALtemp23:
// write entire quad w/ no side-effect // write entire quad w/ no side-effect
old = ipr[idx]; old = ipr[idx];
ipr[idx] = val; ipr[idx] = val;
@ -349,23 +332,23 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
#endif #endif
break; break;
case AlphaISA::IPR_DTB_PTE: case IPR_DTB_PTE:
// write entire quad w/ no side-effect, tag is forthcoming // write entire quad w/ no side-effect, tag is forthcoming
ipr[idx] = val; ipr[idx] = val;
break; break;
case AlphaISA::IPR_EXC_ADDR: case IPR_EXC_ADDR:
// second least significant bit in PC is always zero // second least significant bit in PC is always zero
ipr[idx] = val & ~2; ipr[idx] = val & ~2;
break; break;
case AlphaISA::IPR_ASTRR: case IPR_ASTRR:
case AlphaISA::IPR_ASTER: case IPR_ASTER:
// only write least significant four bits - privilege mask // only write least significant four bits - privilege mask
ipr[idx] = val & 0xf; ipr[idx] = val & 0xf;
break; break;
case AlphaISA::IPR_IPLR: case IPR_IPLR:
#ifdef DEBUG #ifdef DEBUG
if (break_ipl != -1 && break_ipl == (val & 0x1f)) if (break_ipl != -1 && break_ipl == (val & 0x1f))
debug_break(); debug_break();
@ -379,175 +362,175 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
#endif #endif
break; break;
case AlphaISA::IPR_DTB_CM: case IPR_DTB_CM:
#if FULL_SYSTEM #if FULL_SYSTEM
if (val & 0x18) { if (val & 0x18) {
if (tc->getKernelStats()) if (tc->getKernelStats())
tc->getKernelStats()->mode(AlphaISA::Kernel::user, tc); tc->getKernelStats()->mode(Kernel::user, tc);
} else { } else {
if (tc->getKernelStats()) if (tc->getKernelStats())
tc->getKernelStats()->mode(AlphaISA::Kernel::kernel, tc); tc->getKernelStats()->mode(Kernel::kernel, tc);
} }
#endif #endif
case AlphaISA::IPR_ICM: case IPR_ICM:
// only write two mode bits - processor mode // only write two mode bits - processor mode
ipr[idx] = val & 0x18; ipr[idx] = val & 0x18;
break; break;
case AlphaISA::IPR_ALT_MODE: case IPR_ALT_MODE:
// only write two mode bits - processor mode // only write two mode bits - processor mode
ipr[idx] = val & 0x18; ipr[idx] = val & 0x18;
break; break;
case AlphaISA::IPR_MCSR: case IPR_MCSR:
// more here after optimization... // more here after optimization...
ipr[idx] = val; ipr[idx] = val;
break; break;
case AlphaISA::IPR_SIRR: case IPR_SIRR:
// only write software interrupt mask // only write software interrupt mask
ipr[idx] = val & 0x7fff0; ipr[idx] = val & 0x7fff0;
break; break;
case AlphaISA::IPR_ICSR: case IPR_ICSR:
ipr[idx] = val & ULL(0xffffff0300); ipr[idx] = val & ULL(0xffffff0300);
break; break;
case AlphaISA::IPR_IVPTBR: case IPR_IVPTBR:
case AlphaISA::IPR_MVPTBR: case IPR_MVPTBR:
ipr[idx] = val & ULL(0xffffffffc0000000); ipr[idx] = val & ULL(0xffffffffc0000000);
break; break;
case AlphaISA::IPR_DC_TEST_CTL: case IPR_DC_TEST_CTL:
ipr[idx] = val & 0x1ffb; ipr[idx] = val & 0x1ffb;
break; break;
case AlphaISA::IPR_DC_MODE: case IPR_DC_MODE:
case AlphaISA::IPR_MAF_MODE: case IPR_MAF_MODE:
ipr[idx] = val & 0x3f; ipr[idx] = val & 0x3f;
break; break;
case AlphaISA::IPR_ITB_ASN: case IPR_ITB_ASN:
ipr[idx] = val & 0x7f0; ipr[idx] = val & 0x7f0;
break; break;
case AlphaISA::IPR_DTB_ASN: case IPR_DTB_ASN:
ipr[idx] = val & ULL(0xfe00000000000000); ipr[idx] = val & ULL(0xfe00000000000000);
break; break;
case AlphaISA::IPR_EXC_SUM: case IPR_EXC_SUM:
case AlphaISA::IPR_EXC_MASK: case IPR_EXC_MASK:
// any write to this register clears it // any write to this register clears it
ipr[idx] = 0; ipr[idx] = 0;
break; break;
case AlphaISA::IPR_INTID: case IPR_INTID:
case AlphaISA::IPR_SL_RCV: case IPR_SL_RCV:
case AlphaISA::IPR_MM_STAT: case IPR_MM_STAT:
case AlphaISA::IPR_ITB_PTE_TEMP: case IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP: case IPR_DTB_PTE_TEMP:
// read-only registers // read-only registers
panic("Tried to write read only ipr %d\n", idx); panic("Tried to write read only ipr %d\n", idx);
case AlphaISA::IPR_HWINT_CLR: case IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT: case IPR_SL_XMIT:
case AlphaISA::IPR_DC_FLUSH: case IPR_DC_FLUSH:
case AlphaISA::IPR_IC_FLUSH: case IPR_IC_FLUSH:
// the following are write only // the following are write only
ipr[idx] = val; ipr[idx] = val;
break; break;
case AlphaISA::IPR_DTB_IA: case IPR_DTB_IA:
// really a control write // really a control write
ipr[idx] = 0; ipr[idx] = 0;
tc->getDTBPtr()->flushAll(); tc->getDTBPtr()->flushAll();
break; break;
case AlphaISA::IPR_DTB_IAP: case IPR_DTB_IAP:
// really a control write // really a control write
ipr[idx] = 0; ipr[idx] = 0;
tc->getDTBPtr()->flushProcesses(); tc->getDTBPtr()->flushProcesses();
break; break;
case AlphaISA::IPR_DTB_IS: case IPR_DTB_IS:
// really a control write // really a control write
ipr[idx] = val; ipr[idx] = val;
tc->getDTBPtr()->flushAddr(val, tc->getDTBPtr()->flushAddr(val,
AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
break; break;
case AlphaISA::IPR_DTB_TAG: { case IPR_DTB_TAG: {
struct AlphaISA::TlbEntry entry; struct TlbEntry entry;
// FIXME: granularity hints NYI... // FIXME: granularity hints NYI...
if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0"); panic("PTE GH field != 0");
// write entire quad // write entire quad
ipr[idx] = val; ipr[idx] = val;
// construct PTE for new entry // construct PTE for new entry
entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB // insert new TAG/PTE value into data TLB
tc->getDTBPtr()->insert(val, entry); tc->getDTBPtr()->insert(val, entry);
} }
break; break;
case AlphaISA::IPR_ITB_PTE: { case IPR_ITB_PTE: {
struct AlphaISA::TlbEntry entry; struct TlbEntry entry;
// FIXME: granularity hints NYI... // FIXME: granularity hints NYI...
if (AlphaISA::ITB_PTE_GH(val) != 0) if (ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0"); panic("PTE GH field != 0");
// write entire quad // write entire quad
ipr[idx] = val; ipr[idx] = val;
// construct PTE for new entry // construct PTE for new entry
entry.ppn = AlphaISA::ITB_PTE_PPN(val); entry.ppn = ITB_PTE_PPN(val);
entry.xre = AlphaISA::ITB_PTE_XRE(val); entry.xre = ITB_PTE_XRE(val);
entry.xwe = 0; entry.xwe = 0;
entry.fonr = AlphaISA::ITB_PTE_FONR(val); entry.fonr = ITB_PTE_FONR(val);
entry.fonw = AlphaISA::ITB_PTE_FONW(val); entry.fonw = ITB_PTE_FONW(val);
entry.asma = AlphaISA::ITB_PTE_ASMA(val); entry.asma = ITB_PTE_ASMA(val);
entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB // insert new TAG/PTE value into data TLB
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry); tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
} }
break; break;
case AlphaISA::IPR_ITB_IA: case IPR_ITB_IA:
// really a control write // really a control write
ipr[idx] = 0; ipr[idx] = 0;
tc->getITBPtr()->flushAll(); tc->getITBPtr()->flushAll();
break; break;
case AlphaISA::IPR_ITB_IAP: case IPR_ITB_IAP:
// really a control write // really a control write
ipr[idx] = 0; ipr[idx] = 0;
tc->getITBPtr()->flushProcesses(); tc->getITBPtr()->flushProcesses();
break; break;
case AlphaISA::IPR_ITB_IS: case IPR_ITB_IS:
// really a control write // really a control write
ipr[idx] = val; ipr[idx] = val;
tc->getITBPtr()->flushAddr(val, tc->getITBPtr()->flushAddr(val,
AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
break; break;
default: default:
@ -560,14 +543,34 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
void void
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) copyIprs(ThreadContext *src, ThreadContext *dest)
{ {
for (int i = 0; i < NumInternalProcRegs; ++i) { for (int i = 0; i < NumInternalProcRegs; ++i) {
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
} }
} }
} // namespace AlphaISA
#if FULL_SYSTEM #if FULL_SYSTEM
using namespace AlphaISA;
Fault
SimpleThread::hwrei()
{
if (!(readPC() & 0x3))
return new UnimplementedOpcodeFault;
setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
if (!misspeculating()) {
if (kernelStats)
kernelStats->hwrei();
}
// FIXME: XXX check for interrupts? XXX
return NoFault;
}
/** /**
* Check for special simulator handling of specific PAL calls. * Check for special simulator handling of specific PAL calls.

14
src/arch/alpha/ev5.hh
View file

@ -48,8 +48,8 @@ const int VAddrImplBits = 43;
const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
const Addr VAddrUnImplMask = ~VAddrImplMask; const Addr VAddrUnImplMask = ~VAddrImplMask;
inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
@ -73,12 +73,12 @@ inline Addr Phys2K0Seg(Addr addr)
addr |= PAddrUncachedBit40; addr |= PAddrUncachedBit40;
} }
#endif #endif
return addr | AlphaISA::K0SegBase; return addr | K0SegBase;
} }
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg) inline Addr DTB_PTE_PPN(uint64_t reg)
{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } { return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@ -88,7 +88,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg) inline Addr ITB_PTE_PPN(uint64_t reg)
{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } { return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
@ -111,8 +111,8 @@ const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
const uint64_t MM_STAT_FONR_MASK = ULL(0x0004); const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
const uint64_t MM_STAT_ACV_MASK = ULL(0x0002); const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
const uint64_t MM_STAT_WR_MASK = ULL(0x0001); const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
const Addr PalBase = 0x4000; const Addr PalBase = 0x4000;
const Addr PalMax = 0x10000; const Addr PalMax = 0x10000;

28
src/arch/alpha/faults.cc
View file

@ -116,15 +116,15 @@ void AlphaFault::invoke(ThreadContext * tc)
// exception restart address // exception restart address
if (setRestartAddress() || !(tc->readPC() & 0x3)) if (setRestartAddress() || !(tc->readPC() & 0x3))
tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC()); tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) { if (skipFaultingInstruction()) {
// traps... skip faulting instruction. // traps... skip faulting instruction.
tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->setMiscRegNoEffect(IPR_EXC_ADDR,
tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4); tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
} }
tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect()); tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst)); tc->setNextPC(tc->readPC() + sizeof(MachInst));
} }
@ -144,17 +144,17 @@ void DtbFault::invoke(ThreadContext * tc)
if (!tc->misspeculating() if (!tc->misspeculating()
&& !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
// set VA register with faulting address // set VA register with faulting address
tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr); tc->setMiscRegNoEffect(IPR_VA, vaddr);
// set MM_STAT register flags // set MM_STAT register flags
tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT, tc->setMiscRegNoEffect(IPR_MM_STAT,
(((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11) (((Opcode(tc->getInst()) & 0x3f) << 11)
| ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6) | ((Ra(tc->getInst()) & 0x1f) << 6)
| (flags & 0x3f))); | (flags & 0x3f)));
// set VA_FORM register with faulting formatted address // set VA_FORM register with faulting formatted address
tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM, tc->setMiscRegNoEffect(IPR_VA_FORM,
tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
} }
AlphaFault::invoke(tc); AlphaFault::invoke(tc);
@ -163,10 +163,10 @@ void DtbFault::invoke(ThreadContext * tc)
void ItbFault::invoke(ThreadContext * tc) void ItbFault::invoke(ThreadContext * tc)
{ {
if (!tc->misspeculating()) { if (!tc->misspeculating()) {
tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc); tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM, tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) | tc->readMiscRegNoEffect(IPR_IVPTBR) |
(AlphaISA::VAddr(pc).vpn() << 3)); (VAddr(pc).vpn() << 3));
} }
AlphaFault::invoke(tc); AlphaFault::invoke(tc);

14
src/arch/alpha/faults.hh
View file

@ -134,11 +134,11 @@ class InterruptFault : public AlphaFault
class DtbFault : public AlphaFault class DtbFault : public AlphaFault
{ {
protected: protected:
AlphaISA::VAddr vaddr; VAddr vaddr;
uint32_t reqFlags; uint32_t reqFlags;
uint64_t flags; uint64_t flags;
public: public:
DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags) DtbFault(VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags) : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
{ } { }
FaultName name() const = 0; FaultName name() const = 0;
@ -156,7 +156,7 @@ class NDtbMissFault : public DtbFault
static FaultVect _vect; static FaultVect _vect;
static FaultStat _count; static FaultStat _count;
public: public:
NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) NDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags) : DtbFault(vaddr, reqFlags, flags)
{ } { }
FaultName name() const {return _name;} FaultName name() const {return _name;}
@ -174,7 +174,7 @@ class PDtbMissFault : public DtbFault
static FaultVect _vect; static FaultVect _vect;
static FaultStat _count; static FaultStat _count;
public: public:
PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) PDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags) : DtbFault(vaddr, reqFlags, flags)
{ } { }
FaultName name() const {return _name;} FaultName name() const {return _name;}
@ -189,7 +189,7 @@ class DtbPageFault : public DtbFault
static FaultVect _vect; static FaultVect _vect;
static FaultStat _count; static FaultStat _count;
public: public:
DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) DtbPageFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags) : DtbFault(vaddr, reqFlags, flags)
{ } { }
FaultName name() const {return _name;} FaultName name() const {return _name;}
@ -204,7 +204,7 @@ class DtbAcvFault : public DtbFault
static FaultVect _vect; static FaultVect _vect;
static FaultStat _count; static FaultStat _count;
public: public:
DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) DtbAcvFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags) : DtbFault(vaddr, reqFlags, flags)
{ } { }
FaultName name() const {return _name;} FaultName name() const {return _name;}
@ -219,7 +219,7 @@ class DtbAlignmentFault : public DtbFault
static FaultVect _vect; static FaultVect _vect;
static FaultStat _count; static FaultStat _count;
public: public:
DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags) DtbAlignmentFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags) : DtbFault(vaddr, reqFlags, flags)
{ } { }
FaultName name() const {return _name;} FaultName name() const {return _name;}

2
src/arch/alpha/idle_event.cc
View file

@ -40,6 +40,6 @@ IdleStartEvent::process(ThreadContext *tc)
{ {
if (tc->getKernelStats()) if (tc->getKernelStats())
tc->getKernelStats()->setIdleProcess( tc->getKernelStats()->setIdleProcess(
tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23), tc); tc->readMiscRegNoEffect(IPR_PALtemp23), tc);
remove(); remove();
} }

2
src/arch/alpha/interrupts.hh
View file

@ -78,7 +78,7 @@ class Interrupts
{ {
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
if (int_num < 0 || int_num >= AlphaISA::NumInterruptLevels) if (int_num < 0 || int_num >= NumInterruptLevels)
panic("int_num out of bounds\n"); panic("int_num out of bounds\n");
if (index < 0 || index >= (int)sizeof(uint64_t) * 8) if (index < 0 || index >= (int)sizeof(uint64_t) * 8)

4
src/arch/alpha/intregfile.cc
View file

@ -37,13 +37,13 @@
namespace AlphaISA namespace AlphaISA
{ {
#if FULL_SYSTEM #if FULL_SYSTEM
const int reg_redir[AlphaISA::NumIntRegs] = { const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15, /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 }; /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
#else #else
const int reg_redir[AlphaISA::NumIntRegs] = { const int reg_redir[NumIntRegs] = {
/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15, /* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,

8
src/arch/alpha/isa/decoder.isa
View file

@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() {
/* Rb is a fake dependency so here is a fun way to get /* Rb is a fake dependency so here is a fun way to get
* the parser to understand that. * the parser to understand that.
*/ */
Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0); Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
#else #else
Ra = curTick; Ra = curTick;
@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() {
0x00: CallPal::call_pal({{ 0x00: CallPal::call_pal({{
if (!palValid || if (!palValid ||
(palPriv (palPriv
&& xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) { && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
// invalid pal function code, or attempt to do privileged // invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode // PAL call in non-kernel mode
fault = new UnimplementedOpcodeFault; fault = new UnimplementedOpcodeFault;
@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() {
bool dopal = xc->simPalCheck(palFunc); bool dopal = xc->simPalCheck(palFunc);
if (dopal) { if (dopal) {
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC); xc->setMiscReg(IPR_EXC_ADDR, NPC);
NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset; NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
} }
} }
}}, IsNonSpeculative); }}, IsNonSpeculative);

4
src/arch/alpha/isa/fp.isa
View file

@ -46,7 +46,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (!AlphaISA::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) { if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault; fault = new FloatEnableFault;
} }
return fault; return fault;
@ -229,7 +229,7 @@ def template FloatingPointExecute {{
%(code)s; %(code)s;
} else { } else {
m5_fesetround(getC99RoundingMode( m5_fesetround(getC99RoundingMode(
xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR))); xc->readMiscRegNoEffect(MISCREG_FPCR)));
%(code)s; %(code)s;
m5_fesetround(M5_FE_TONEAREST); m5_fesetround(M5_FE_TONEAREST);
} }

6
src/arch/alpha/isa/main.isa
View file

@ -173,11 +173,11 @@ def operands {{
# Int regs default to unsigned, but code should not count on this. # Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should # For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'. # explicitly specify '.uq'.
'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA', 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
'IsInteger', 1), 'IsInteger', 1),
'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB', 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
'IsInteger', 2), 'IsInteger', 2),
'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC', 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
'IsInteger', 3), 'IsInteger', 3),
'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),

6
src/arch/alpha/kernel_stats.cc
View file

@ -152,7 +152,7 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
void void
Statistics::mode(cpu_mode newmode, ThreadContext *tc) Statistics::mode(cpu_mode newmode, ThreadContext *tc)
{ {
Addr pcbb = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23); Addr pcbb = tc->readMiscRegNoEffect(IPR_PALtemp23);
if (newmode == kernel && pcbb == idleProcess) if (newmode == kernel && pcbb == idleProcess)
newmode = idle; newmode = idle;
@ -213,5 +213,5 @@ Statistics::unserialize(Checkpoint *cp, const string &section)
themode = (cpu_mode)exemode; themode = (cpu_mode)exemode;
} }
} /* end namespace AlphaISA::Kernel */ } // namespace Kernel
} /* end namespace AlphaISA */ } // namespace AlphaISA

4
src/arch/alpha/kernel_stats.hh
View file

@ -90,7 +90,7 @@ class Statistics : public ::Kernel::Statistics
void unserialize(Checkpoint *cp, const std::string &section); void unserialize(Checkpoint *cp, const std::string &section);
}; };
} /* end namespace AlphaISA::Kernel */ } // namespace Kernel
} /* end namespace AlphaISA */ } // namespace AlphaISA
#endif // __ARCH_ALPHA_KERNEL_STATS_HH__ #endif // __ARCH_ALPHA_KERNEL_STATS_HH__

6
src/arch/alpha/pagetable.hh
View file

@ -54,11 +54,11 @@ namespace AlphaISA {
Addr offset() const { return addr & PageOffset; } Addr offset() const { return addr & PageOffset; }
Addr level3() const Addr level3() const
{ return AlphaISA::PteAddr(addr >> PageShift); } { return PteAddr(addr >> PageShift); }
Addr level2() const Addr level2() const
{ return AlphaISA::PteAddr(addr >> NPtePageShift + PageShift); } { return PteAddr(addr >> NPtePageShift + PageShift); }
Addr level1() const Addr level1() const
{ return AlphaISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); } { return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
}; };
struct PageTableEntry struct PageTableEntry

18
src/arch/alpha/regfile.cc
View file

@ -70,7 +70,7 @@ namespace AlphaISA
} }
// Then loop through the floating point registers. // Then loop through the floating point registers.
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { for (int i = 0; i < NumFloatRegs; ++i) {
dest->setFloatRegBits(i, src->readFloatRegBits(i)); dest->setFloatRegBits(i, src->readFloatRegBits(i));
} }
@ -85,14 +85,14 @@ namespace AlphaISA
void void
copyMiscRegs(ThreadContext *src, ThreadContext *dest) copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{ {
dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, dest->setMiscRegNoEffect(MISCREG_FPCR,
src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)); src->readMiscRegNoEffect(MISCREG_FPCR));
dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, dest->setMiscRegNoEffect(MISCREG_UNIQ,
src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ)); src->readMiscRegNoEffect(MISCREG_UNIQ));
dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG)); src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR, dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR)); src->readMiscRegNoEffect(MISCREG_LOCKADDR));
copyIprs(src, dest); copyIprs(src, dest);
} }

36
src/arch/alpha/remote_gdb.cc
View file

@ -161,12 +161,12 @@ RemoteGDB::acc(Addr va, size_t len)
#else #else
Addr last_va; Addr last_va;
va = AlphaISA::TruncPage(va); va = TruncPage(va);
last_va = AlphaISA::RoundPage(va + len); last_va = RoundPage(va + len);
do { do {
if (AlphaISA::IsK0Seg(va)) { if (IsK0Seg(va)) {
if (va < (AlphaISA::K0SegBase + pmem->size())) { if (va < (K0SegBase + pmem->size())) {
DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
"%#x < K0SEG + size\n", va); "%#x < K0SEG + size\n", va);
return true; return true;
@ -184,16 +184,16 @@ RemoteGDB::acc(Addr va, size_t len)
* but there is no easy way to do it. * but there is no easy way to do it.
*/ */
if (AlphaISA::PcPAL(va) || va < 0x10000) if (PcPAL(va) || va < 0x10000)
return true; return true;
Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
AlphaISA::PageTableEntry pte = AlphaISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); PageTableEntry pte = kernel_pte_lookup(context->getPhysPort(), ptbr, va);
if (!pte.valid()) { if (!pte.valid()) {
DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
return false; return false;
} }
va += AlphaISA::PageBytes; va += PageBytes;
} while (va < last_va); } while (va < last_va);
DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
@ -214,18 +214,18 @@ RemoteGDB::getregs()
gdbregs.regs[KGDB_REG_PC] = context->readPC(); gdbregs.regs[KGDB_REG_PC] = context->readPC();
// @todo: Currently this is very Alpha specific. // @todo: Currently this is very Alpha specific.
if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { for (int i = 0; i < NumIntArchRegs; ++i) {
gdbregs.regs[i] = context->readIntReg(AlphaISA::reg_redir[i]); gdbregs.regs[i] = context->readIntReg(reg_redir[i]);
} }
} else { } else {
for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { for (int i = 0; i < NumIntArchRegs; ++i) {
gdbregs.regs[i] = context->readIntReg(i); gdbregs.regs[i] = context->readIntReg(i);
} }
} }
#ifdef KGDB_FP_REGS #ifdef KGDB_FP_REGS
for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) { for (int i = 0; i < NumFloatArchRegs; ++i) {
gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i); gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
} }
#endif #endif
@ -241,18 +241,18 @@ void
RemoteGDB::setregs() RemoteGDB::setregs()
{ {
// @todo: Currently this is very Alpha specific. // @todo: Currently this is very Alpha specific.
if (AlphaISA::PcPAL(gdbregs.regs[KGDB_REG_PC])) { if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { for (int i = 0; i < NumIntArchRegs; ++i) {
context->setIntReg(AlphaISA::reg_redir[i], gdbregs.regs[i]); context->setIntReg(reg_redir[i], gdbregs.regs[i]);
} }
} else { } else {
for (int i = 0; i < AlphaISA::NumIntArchRegs; ++i) { for (int i = 0; i < NumIntArchRegs; ++i) {
context->setIntReg(i, gdbregs.regs[i]); context->setIntReg(i, gdbregs.regs[i]);
} }
} }
#ifdef KGDB_FP_REGS #ifdef KGDB_FP_REGS
for (int i = 0; i < AlphaISA::NumFloatArchRegs; ++i) { for (int i = 0; i < NumFloatArchRegs; ++i) {
context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]); context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]);
} }
#endif #endif

16
src/arch/alpha/stacktrace.cc
View file

@ -142,7 +142,7 @@ namespace AlphaISA
{ {
tc = _tc; tc = _tc;
bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; bool usermode = (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
Addr pc = tc->readNextPC(); Addr pc = tc->readNextPC();
bool kernel = tc->getSystemPtr()->kernelStart <= pc && bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
@ -159,7 +159,7 @@ namespace AlphaISA
} }
SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
Addr ksp = tc->readIntReg(AlphaISA::StackPointerReg); Addr ksp = tc->readIntReg(StackPointerReg);
Addr bottom = ksp & ~0x3fff; Addr bottom = ksp & ~0x3fff;
Addr addr; Addr addr;
@ -215,22 +215,22 @@ namespace AlphaISA
bool bool
StackTrace::isEntry(Addr addr) StackTrace::isEntry(Addr addr)
{ {
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp12))
return true; return true;
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp7))
return true; return true;
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp11))
return true; return true;
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp21))
return true; return true;
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp9))
return true; return true;
if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2)) if (addr == tc->readMiscRegNoEffect(IPR_PALtemp2))
return true; return true;
return false; return false;

2
src/arch/alpha/stacktrace.hh
View file

@ -61,8 +61,6 @@ namespace AlphaISA
class StackTrace class StackTrace
{ {
protected:
typedef AlphaISA::MachInst MachInst;
private: private:
ThreadContext *tc; ThreadContext *tc;
std::vector<Addr> stack; std::vector<Addr> stack;

13
src/arch/alpha/system.cc
View file

@ -42,8 +42,7 @@
#include "params/AlphaSystem.hh" #include "params/AlphaSystem.hh"
#include "sim/byteswap.hh" #include "sim/byteswap.hh"
using namespace AlphaISA;
using namespace LittleEndianGuest;
AlphaSystem::AlphaSystem(Params *p) AlphaSystem::AlphaSystem(Params *p)
: System(p) : System(p)
@ -67,8 +66,8 @@ AlphaSystem::AlphaSystem(Params *p)
// Load program sections into memory // Load program sections into memory
pal->loadSections(&functionalPort, AlphaISA::LoadAddrMask); pal->loadSections(&functionalPort, LoadAddrMask);
console->loadSections(&functionalPort, AlphaISA::LoadAddrMask); console->loadSections(&functionalPort, LoadAddrMask);
// load symbols // load symbols
if (!console->loadGlobalSymbols(consoleSymtab)) if (!console->loadGlobalSymbols(consoleSymtab))
@ -172,11 +171,11 @@ AlphaSystem::fixFuncEventAddr(Addr addr)
const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16); const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16);
uint32_t i1 = virtPort.read<uint32_t>(addr); uint32_t i1 = virtPort.read<uint32_t>(addr);
uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(AlphaISA::MachInst)); uint32_t i2 = virtPort.read<uint32_t>(addr + sizeof(MachInst));
if ((i1 & inst_mask) == gp_ldah_pattern && if ((i1 & inst_mask) == gp_ldah_pattern &&
(i2 & inst_mask) == gp_lda_pattern) { (i2 & inst_mask) == gp_lda_pattern) {
Addr new_addr = addr + 2* sizeof(AlphaISA::MachInst); Addr new_addr = addr + 2* sizeof(MachInst);
DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr); DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
return new_addr; return new_addr;
} else { } else {
@ -190,7 +189,7 @@ AlphaSystem::setAlphaAccess(Addr access)
{ {
Addr addr = 0; Addr addr = 0;
if (consoleSymtab->findAddress("m5AlphaAccess", addr)) { if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
virtPort.write(addr, htog(AlphaISA::Phys2K0Seg(access))); virtPort.write(addr, htog(Phys2K0Seg(access)));
} else } else
panic("could not find m5AlphaAccess\n"); panic("could not find m5AlphaAccess\n");
} }

2
src/arch/alpha/tlb.cc
View file

@ -622,7 +622,7 @@ TLB::index(bool advance)
return *entry; return *entry;
} }
/* end namespace AlphaISA */ } } // namespace AlphaISA
AlphaISA::ITB * AlphaISA::ITB *
AlphaITBParams::create() AlphaITBParams::create()

4
src/arch/alpha/tlb.hh
View file

@ -88,8 +88,8 @@ namespace AlphaISA
// static helper functions... really EV5 VM traits // static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) { static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1 // unimplemented bits must be all 0 or all 1
Addr unimplBits = vaddr & AlphaISA::VAddrUnImplMask; Addr unimplBits = vaddr & VAddrUnImplMask;
return (unimplBits == 0) || (unimplBits == AlphaISA::VAddrUnImplMask); return (unimplBits == 0) || (unimplBits == VAddrUnImplMask);
} }
static Fault checkCacheability(RequestPtr &req, bool itb = false); static Fault checkCacheability(RequestPtr &req, bool itb = false);

2
src/arch/alpha/utility.hh
View file

@ -46,7 +46,7 @@ namespace AlphaISA
inline bool inline bool
inUserMode(ThreadContext *tc) inUserMode(ThreadContext *tc)
{ {
return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
} }
inline bool inline bool

37
src/arch/alpha/vtophys.cc
View file

@ -40,27 +40,28 @@
#include "mem/vport.hh" #include "mem/vport.hh"
using namespace std; using namespace std;
using namespace AlphaISA;
AlphaISA::PageTableEntry namespace AlphaISA {
AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr)
PageTableEntry
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
{ {
Addr level1_pte = ptbr + vaddr.level1(); Addr level1_pte = ptbr + vaddr.level1();
AlphaISA::PageTableEntry level1 = mem->read<uint64_t>(level1_pte); PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
if (!level1.valid()) { if (!level1.valid()) {
DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
return 0; return 0;
} }
Addr level2_pte = level1.paddr() + vaddr.level2(); Addr level2_pte = level1.paddr() + vaddr.level2();
AlphaISA::PageTableEntry level2 = mem->read<uint64_t>(level2_pte); PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
if (!level2.valid()) { if (!level2.valid()) {
DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
return 0; return 0;
} }
Addr level3_pte = level2.paddr() + vaddr.level3(); Addr level3_pte = level2.paddr() + vaddr.level3();
AlphaISA::PageTableEntry level3 = mem->read<uint64_t>(level3_pte); PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
if (!level3.valid()) { if (!level3.valid()) {
DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
return 0; return 0;
@ -69,13 +70,13 @@ AlphaISA::kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vadd
} }
Addr Addr
AlphaISA::vtophys(Addr vaddr) vtophys(Addr vaddr)
{ {
Addr paddr = 0; Addr paddr = 0;
if (AlphaISA::IsUSeg(vaddr)) if (IsUSeg(vaddr))
DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
else if (AlphaISA::IsK0Seg(vaddr)) else if (IsK0Seg(vaddr))
paddr = AlphaISA::K0Seg2Phys(vaddr); paddr = K0Seg2Phys(vaddr);
else else
panic("vtophys: ptbr is not set on virtual lookup"); panic("vtophys: ptbr is not set on virtual lookup");
@ -85,22 +86,22 @@ AlphaISA::vtophys(Addr vaddr)
} }
Addr Addr
AlphaISA::vtophys(ThreadContext *tc, Addr addr) vtophys(ThreadContext *tc, Addr addr)
{ {
AlphaISA::VAddr vaddr = addr; VAddr vaddr = addr;
Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
Addr paddr = 0; Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code //@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging? //so I put it back in. Perhaps something to do with gdb debugging?
if (AlphaISA::PcPAL(vaddr) && (vaddr < AlphaISA::PalMax)) { if (PcPAL(vaddr) && (vaddr < PalMax)) {
paddr = vaddr & ~ULL(1); paddr = vaddr & ~ULL(1);
} else { } else {
if (AlphaISA::IsK0Seg(vaddr)) { if (IsK0Seg(vaddr)) {
paddr = AlphaISA::K0Seg2Phys(vaddr); paddr = K0Seg2Phys(vaddr);
} else if (!ptbr) { } else if (!ptbr) {
paddr = vaddr; paddr = vaddr;
} else { } else {
AlphaISA::PageTableEntry pte = PageTableEntry pte =
kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
if (pte.valid()) if (pte.valid())
paddr = pte.paddr() | vaddr.offset(); paddr = pte.paddr() | vaddr.offset();
@ -113,3 +114,5 @@ AlphaISA::vtophys(ThreadContext *tc, Addr addr)
return paddr; return paddr;
} }
} // namespace AlphaISA

2
src/arch/alpha/vtophys.hh
View file

@ -42,7 +42,7 @@ class FunctionalPort;
namespace AlphaISA { namespace AlphaISA {
PageTableEntry PageTableEntry
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr); kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr);
Addr vtophys(Addr vaddr); Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr); Addr vtophys(ThreadContext *tc, Addr vaddr);