ruby: move files from ruby/system to ruby/structures
The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. --HG-- rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
This commit is contained in:
parent
01f792a367
commit
82d136285d
60 changed files with 90 additions and 159 deletions
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@ -118,21 +118,21 @@ MakeInclude('slicc_interface/NetworkMessage.hh')
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MakeInclude('slicc_interface/RubyRequest.hh')
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# External types
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MakeInclude('buffers/MessageBuffer.hh')
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MakeInclude('common/Address.hh')
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MakeInclude('common/DataBlock.hh')
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MakeInclude('common/MachineID.hh')
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MakeInclude('common/NetDest.hh')
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MakeInclude('common/Set.hh')
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MakeInclude('filters/GenericBloomFilter.hh')
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MakeInclude('network/MessageBuffer.hh')
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MakeInclude('structures/Prefetcher.hh')
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MakeInclude('system/CacheMemory.hh')
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MakeInclude('structures/CacheMemory.hh')
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MakeInclude('system/DMASequencer.hh')
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MakeInclude('system/DirectoryMemory.hh')
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MakeInclude('system/MachineID.hh')
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MakeInclude('system/MemoryControl.hh')
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MakeInclude('system/WireBuffer.hh')
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MakeInclude('system/PerfectCacheMemory.hh')
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MakeInclude('system/PersistentTable.hh')
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MakeInclude('structures/DirectoryMemory.hh')
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MakeInclude('structures/MemoryControl.hh')
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MakeInclude('structures/WireBuffer.hh')
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MakeInclude('structures/PerfectCacheMemory.hh')
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MakeInclude('structures/PersistentTable.hh')
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MakeInclude('system/Sequencer.hh')
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MakeInclude('system/TBETable.hh')
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MakeInclude('system/TimerTable.hh')
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MakeInclude('structures/TBETable.hh')
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MakeInclude('structures/TimerTable.hh')
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@ -1,37 +0,0 @@
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# -*- mode:python -*-
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# Copyright (c) 2009 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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if env['PROTOCOL'] == 'None':
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Return()
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Source('MessageBuffer.cc')
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Source('MessageBufferNode.cc')
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@ -38,7 +38,7 @@
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#include <vector>
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#include "mem/ruby/common/Set.hh"
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/ruby/common/MachineID.hh"
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class NetDest
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{
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@ -32,7 +32,7 @@
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#include "base/misc.hh"
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#include "base/stl_helpers.hh"
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#include "debug/RubyQueue.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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@ -41,11 +41,11 @@
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#include <string>
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#include <vector>
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#include "mem/packet.hh"
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#include "mem/ruby/buffers/MessageBufferNode.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/network/MessageBufferNode.hh"
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#include "mem/ruby/slicc_interface/Message.hh"
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#include "mem/packet.hh"
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class MessageBuffer
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{
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@ -26,7 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/buffers/MessageBufferNode.hh"
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#include "mem/ruby/network/MessageBufferNode.hh"
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void
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MessageBufferNode::print(std::ostream& out) const
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@ -39,5 +39,7 @@ SimObject('Network.py')
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Source('BasicLink.cc')
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Source('BasicRouter.cc')
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Source('MessageBuffer.cc')
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Source('MessageBufferNode.cc')
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Source('Network.cc')
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Source('Topology.cc')
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@ -28,8 +28,8 @@
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* Authors: Niket Agarwal
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*/
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/garnet/BaseGarnetNetwork.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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using namespace std;
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@ -34,7 +34,7 @@
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#include "base/cast.hh"
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#include "base/stl_helpers.hh"
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#include "debug/RubyNetwork.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh"
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#include "mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh"
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#include "mem/ruby/slicc_interface/NetworkMessage.hh"
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@ -34,7 +34,7 @@
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#include "base/cast.hh"
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#include "base/stl_helpers.hh"
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#include "debug/RubyNetwork.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh"
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#include "mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh"
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#include "mem/ruby/slicc_interface/NetworkMessage.hh"
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@ -30,7 +30,7 @@
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#include "base/cast.hh"
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#include "debug/RubyNetwork.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/simple/PerfectSwitch.hh"
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#include "mem/ruby/network/simple/SimpleNetwork.hh"
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#include "mem/ruby/network/simple/Switch.hh"
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@ -31,8 +31,8 @@
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#include "base/cast.hh"
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#include "base/stl_helpers.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/common/NetDest.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/simple/SimpleLink.hh"
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#include "mem/ruby/network/simple/SimpleNetwork.hh"
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#include "mem/ruby/network/simple/Switch.hh"
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@ -30,7 +30,7 @@
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#include "base/cast.hh"
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#include "base/stl_helpers.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/simple/PerfectSwitch.hh"
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#include "mem/ruby/network/simple/SimpleNetwork.hh"
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#include "mem/ruby/network/simple/Switch.hh"
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@ -31,8 +31,8 @@
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#include "base/cast.hh"
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#include "base/cprintf.hh"
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#include "debug/RubyNetwork.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/network/simple/Throttle.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/slicc_interface/NetworkMessage.hh"
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#include "mem/ruby/system/System.hh"
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@ -57,7 +57,7 @@
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#include "mem/protocol/RubyAccessMode.hh"
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#include "mem/protocol/RubyRequestType.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/ruby/common/MachineID.hh"
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#include "params/RubySystem.hh"
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class RubyRequest;
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@ -1,36 +0,0 @@
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# -*- mode:python -*-
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# Copyright (c) 2009 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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if env['PROTOCOL'] == 'None':
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Return()
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Source('CacheRecorder.cc')
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@ -34,14 +34,14 @@
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#include "base/callback.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/ruby/common/MachineID.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/recorder/CacheRecorder.hh"
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "mem/packet.hh"
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#include "params/RubyController.hh"
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#include "sim/clocked_object.hh"
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@ -31,9 +31,9 @@
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#include "mem/protocol/MachineType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/MachineID.hh"
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#include "mem/ruby/common/NetDest.hh"
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#include "mem/ruby/system/DirectoryMemory.hh"
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/ruby/structures/DirectoryMemory.hh"
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// used to determine the home directory
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// returns a value between 0 and total_directories_within_the_system
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@ -30,7 +30,7 @@
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*/
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#include "base/intmath.hh"
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#include "mem/ruby/system/BankedArray.hh"
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#include "mem/ruby/structures/BankedArray.hh"
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#include "mem/ruby/system/System.hh"
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BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
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@ -34,7 +34,7 @@ from Controller import RubyController
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class RubyCache(SimObject):
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type = 'RubyCache'
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cxx_class = 'CacheMemory'
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cxx_header = "mem/ruby/system/CacheMemory.hh"
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cxx_header = "mem/ruby/structures/CacheMemory.hh"
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size = Param.MemorySize("capacity in bytes");
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latency = Param.Cycles("");
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assoc = Param.Int("");
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@ -32,7 +32,7 @@
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#include "debug/RubyResourceStalls.hh"
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#include "debug/RubyStats.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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#include "mem/ruby/structures/CacheMemory.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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@ -34,16 +34,16 @@
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#include "base/hashmap.hh"
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#include "base/statistics.hh"
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#include "mem/protocol/CacheResourceType.hh"
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#include "mem/protocol/CacheRequestType.hh"
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#include "mem/protocol/CacheResourceType.hh"
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#include "mem/protocol/RubyRequest.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/recorder/CacheRecorder.hh"
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#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
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#include "mem/ruby/system/BankedArray.hh"
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#include "mem/ruby/system/LRUPolicy.hh"
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#include "mem/ruby/system/PseudoLRUPolicy.hh"
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#include "mem/ruby/structures/BankedArray.hh"
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#include "mem/ruby/structures/LRUPolicy.hh"
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#include "mem/ruby/structures/PseudoLRUPolicy.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "params/RubyCache.hh"
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#include "sim/sim_object.hh"
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@ -30,7 +30,7 @@
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#include "debug/RubyCache.hh"
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#include "debug/RubyStats.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
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#include "mem/ruby/system/DirectoryMemory.hh"
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#include "mem/ruby/structures/DirectoryMemory.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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#include <iostream>
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#include <string>
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#include "mem/ruby/common/Address.hh"
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#include "mem/protocol/DirectoryRequestType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/slicc_interface/AbstractEntry.hh"
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#include "mem/ruby/system/MemoryVector.hh"
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#include "mem/ruby/system/SparseMemory.hh"
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#include "mem/ruby/structures/MemoryVector.hh"
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#include "mem/ruby/structures/SparseMemory.hh"
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#include "params/RubyDirectoryMemory.hh"
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#include "sim/sim_object.hh"
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class RubyDirectoryMemory(SimObject):
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type = 'RubyDirectoryMemory'
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cxx_class = 'DirectoryMemory'
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cxx_header = "mem/ruby/system/DirectoryMemory.hh"
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cxx_header = "mem/ruby/structures/DirectoryMemory.hh"
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version = Param.Int(0, "")
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size = Param.MemorySize("1GB", "capacity in bytes")
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use_map = Param.Bool(False, "enable sparse memory")
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#ifndef __MEM_RUBY_SYSTEM_LRUPOLICY_HH__
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#define __MEM_RUBY_SYSTEM_LRUPOLICY_HH__
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#include "mem/ruby/system/AbstractReplacementPolicy.hh"
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#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
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/* Simple true LRU replacement policy */
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#include "debug/RubyStats.hh"
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#include "mem/ruby/common/Global.hh"
|
||||
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
|
||||
#include "mem/ruby/system/MemoryControl.hh"
|
||||
#include "mem/ruby/structures/MemoryControl.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
||||
using namespace std;
|
|
@ -37,7 +37,7 @@
|
|||
#include "mem/protocol/MemoryControlRequestType.hh"
|
||||
#include "mem/ruby/common/Consumer.hh"
|
||||
#include "mem/ruby/slicc_interface/Message.hh"
|
||||
#include "mem/ruby/system/MemoryNode.hh"
|
||||
#include "mem/ruby/structures/MemoryNode.hh"
|
||||
#include "params/MemoryControl.hh"
|
||||
#include "sim/clocked_object.hh"
|
||||
|
|
@ -34,6 +34,6 @@ class MemoryControl(ClockedObject):
|
|||
abstract = True
|
||||
type = 'MemoryControl'
|
||||
cxx_class = 'MemoryControl'
|
||||
cxx_header = "mem/ruby/system/MemoryControl.hh"
|
||||
cxx_header = "mem/ruby/structures/MemoryControl.hh"
|
||||
version = Param.Int("");
|
||||
ruby_system = Param.RubySystem("")
|
|
@ -26,7 +26,7 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "mem/ruby/system/MemoryNode.hh"
|
||||
#include "mem/ruby/structures/MemoryNode.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "mem/ruby/system/PersistentTable.hh"
|
||||
#include "mem/ruby/structures/PersistentTable.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
@ -34,8 +34,8 @@
|
|||
#include "base/hashmap.hh"
|
||||
#include "mem/protocol/AccessType.hh"
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/common/MachineID.hh"
|
||||
#include "mem/ruby/common/NetDest.hh"
|
||||
#include "mem/ruby/system/MachineID.hh"
|
||||
|
||||
class PersistentTableEntry
|
||||
{
|
|
@ -34,8 +34,8 @@
|
|||
#include <bitset>
|
||||
|
||||
#include "base/statistics.hh"
|
||||
#include "mem/ruby/buffers/MessageBuffer.hh"
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/network/MessageBuffer.hh"
|
||||
#include "mem/ruby/slicc_interface/AbstractController.hh"
|
||||
#include "mem/ruby/slicc_interface/RubyRequest.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#ifndef __MEM_RUBY_SYSTEM_PSEUDOLRUPOLICY_HH__
|
||||
#define __MEM_RUBY_SYSTEM_PSEUDOLRUPOLICY_HH__
|
||||
|
||||
#include "mem/ruby/system/AbstractReplacementPolicy.hh"
|
||||
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
|
||||
|
||||
/**
|
||||
* Implementation of tree-based pseudo-LRU replacement
|
|
@ -113,7 +113,7 @@
|
|||
#include "mem/ruby/profiler/Profiler.hh"
|
||||
#include "mem/ruby/slicc_interface/NetworkMessage.hh"
|
||||
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
|
||||
#include "mem/ruby/system/RubyMemoryControl.hh"
|
||||
#include "mem/ruby/structures/RubyMemoryControl.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
||||
using namespace std;
|
|
@ -40,8 +40,8 @@
|
|||
#include "mem/ruby/common/Global.hh"
|
||||
#include "mem/ruby/profiler/MemCntrlProfiler.hh"
|
||||
#include "mem/ruby/slicc_interface/Message.hh"
|
||||
#include "mem/ruby/system/MemoryControl.hh"
|
||||
#include "mem/ruby/system/MemoryNode.hh"
|
||||
#include "mem/ruby/structures/MemoryControl.hh"
|
||||
#include "mem/ruby/structures/MemoryNode.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "params/RubyMemoryControl.hh"
|
||||
#include "sim/sim_object.hh"
|
|
@ -34,7 +34,7 @@ from MemoryControl import MemoryControl
|
|||
class RubyMemoryControl(MemoryControl):
|
||||
type = 'RubyMemoryControl'
|
||||
cxx_class = 'RubyMemoryControl'
|
||||
cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
|
||||
cxx_header = "mem/ruby/structures/RubyMemoryControl.hh"
|
||||
version = Param.Int("");
|
||||
|
||||
banks_per_rank = Param.Int(8, "");
|
|
@ -33,5 +33,21 @@ Import('*')
|
|||
if env['PROTOCOL'] == 'None':
|
||||
Return()
|
||||
|
||||
SimObject('Cache.py')
|
||||
SimObject('DirectoryMemory.py')
|
||||
SimObject('MemoryControl.py')
|
||||
SimObject('RubyMemoryControl.py')
|
||||
SimObject('RubyPrefetcher.py')
|
||||
SimObject('WireBuffer.py')
|
||||
|
||||
Source('DirectoryMemory.cc')
|
||||
Source('SparseMemory.cc')
|
||||
Source('CacheMemory.cc')
|
||||
Source('MemoryControl.cc')
|
||||
Source('WireBuffer.cc')
|
||||
Source('RubyMemoryControl.cc')
|
||||
Source('MemoryNode.cc')
|
||||
Source('PersistentTable.cc')
|
||||
Source('Prefetcher.cc')
|
||||
Source('TimerTable.cc')
|
||||
Source('BankedArray.cc')
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
#include <queue>
|
||||
|
||||
#include "debug/RubyCache.hh"
|
||||
#include "mem/ruby/system/SparseMemory.hh"
|
||||
#include "mem/ruby/structures/SparseMemory.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
||||
using namespace std;
|
|
@ -36,8 +36,8 @@
|
|||
#include "base/hashmap.hh"
|
||||
#include "base/statistics.hh"
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/recorder/CacheRecorder.hh"
|
||||
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
|
||||
#include "mem/ruby/system/CacheRecorder.hh"
|
||||
|
||||
typedef void* SparseMemEntry;
|
||||
typedef m5::hash_map<Address, SparseMemEntry> SparseMapType;
|
|
@ -27,8 +27,8 @@
|
|||
*/
|
||||
|
||||
#include "mem/ruby/common/Global.hh"
|
||||
#include "mem/ruby/structures/TimerTable.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "mem/ruby/system/TimerTable.hh"
|
||||
|
||||
TimerTable::TimerTable()
|
||||
: m_next_time(0)
|
|
@ -35,8 +35,8 @@
|
|||
#include "base/cprintf.hh"
|
||||
#include "base/stl_helpers.hh"
|
||||
#include "mem/ruby/common/Global.hh"
|
||||
#include "mem/ruby/structures/WireBuffer.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "mem/ruby/system/WireBuffer.hh"
|
||||
|
||||
using namespace std;
|
||||
|
|
@ -36,8 +36,8 @@
|
|||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "mem/ruby/buffers/MessageBufferNode.hh"
|
||||
#include "mem/ruby/common/Consumer.hh"
|
||||
#include "mem/ruby/network/MessageBufferNode.hh"
|
||||
#include "params/RubyWireBuffer.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
|
@ -32,4 +32,4 @@ from m5.SimObject import SimObject
|
|||
class RubyWireBuffer(SimObject):
|
||||
type = 'RubyWireBuffer'
|
||||
cxx_class = 'WireBuffer'
|
||||
cxx_header = "mem/ruby/system/WireBuffer.hh"
|
||||
cxx_header = "mem/ruby/structures/WireBuffer.hh"
|
|
@ -28,7 +28,7 @@
|
|||
*/
|
||||
|
||||
#include "debug/RubyCacheTrace.hh"
|
||||
#include "mem/ruby/recorder/CacheRecorder.hh"
|
||||
#include "mem/ruby/system/CacheRecorder.hh"
|
||||
#include "mem/ruby/system/Sequencer.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
#include <string>
|
||||
|
||||
#include "mem/protocol/RequestStatus.hh"
|
||||
#include "mem/ruby/buffers/MessageBuffer.hh"
|
||||
#include "mem/ruby/network/MessageBuffer.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/tport.hh"
|
||||
|
|
|
@ -33,26 +33,12 @@ Import('*')
|
|||
if env['PROTOCOL'] == 'None':
|
||||
Return()
|
||||
|
||||
SimObject('Cache.py')
|
||||
SimObject('Sequencer.py')
|
||||
SimObject('DirectoryMemory.py')
|
||||
SimObject('MemoryControl.py')
|
||||
SimObject('WireBuffer.py')
|
||||
SimObject('RubySystem.py')
|
||||
SimObject('RubyMemoryControl.py')
|
||||
|
||||
Source('CacheRecorder.cc')
|
||||
Source('DMASequencer.cc')
|
||||
Source('DirectoryMemory.cc')
|
||||
Source('SparseMemory.cc')
|
||||
Source('CacheMemory.cc')
|
||||
Source('MemoryControl.cc')
|
||||
Source('WireBuffer.cc')
|
||||
Source('RubyMemoryControl.cc')
|
||||
Source('MemoryNode.cc')
|
||||
Source('PersistentTable.cc')
|
||||
Source('RubyPort.cc')
|
||||
Source('RubyPortProxy.cc')
|
||||
Source('Sequencer.cc')
|
||||
Source('System.cc')
|
||||
Source('TimerTable.cc')
|
||||
Source('BankedArray.cc')
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
#include "mem/protocol/RubyRequestType.hh"
|
||||
#include "mem/protocol/SequencerRequestType.hh"
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/system/CacheMemory.hh"
|
||||
#include "mem/ruby/structures/CacheMemory.hh"
|
||||
#include "mem/ruby/system/RubyPort.hh"
|
||||
#include "params/RubySequencer.hh"
|
||||
|
||||
|
|
|
@ -37,13 +37,13 @@
|
|||
|
||||
#include "base/callback.hh"
|
||||
#include "base/output.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/ruby/profiler/Profiler.hh"
|
||||
#include "mem/ruby/recorder/CacheRecorder.hh"
|
||||
#include "mem/ruby/slicc_interface/AbstractController.hh"
|
||||
#include "mem/ruby/system/MemoryControl.hh"
|
||||
#include "mem/ruby/system/MemoryVector.hh"
|
||||
#include "mem/ruby/system/SparseMemory.hh"
|
||||
#include "mem/ruby/structures/MemoryControl.hh"
|
||||
#include "mem/ruby/structures/MemoryVector.hh"
|
||||
#include "mem/ruby/structures/SparseMemory.hh"
|
||||
#include "mem/ruby/system/CacheRecorder.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "params/RubySystem.hh"
|
||||
#include "sim/clocked_object.hh"
|
||||
|
||||
|
|
|
@ -585,7 +585,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
|
|||
for enum in self.enums.itervalues():
|
||||
if enum.get("Primary"):
|
||||
code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
|
||||
code('#include "mem/ruby/system/MachineID.hh"')
|
||||
code('#include "mem/ruby/common/MachineID.hh"')
|
||||
|
||||
code('''
|
||||
// Code for output operator
|
||||
|
|
Loading…
Reference in a new issue