Changed new linux stuff to work with new FunctionalMemory interface and
some sundry problems with new interface dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.cc: dev/tsunami_uart.hh: Fixed to use new FunctionalMemory interface --HG-- extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
This commit is contained in:
parent
eac2d6a668
commit
81d5ffe7de
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@ -51,10 +51,10 @@
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using namespace std;
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using namespace std;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
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SimpleDisk *d, int size, System *system,
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SimpleDisk *d, System *system,
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BaseCPU *cpu, TsunamiIO *clock, int num_cpus,
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BaseCPU *cpu, TsunamiIO *clock, int num_cpus,
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Addr addr, Addr mask, MemoryController *mmu)
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Addr a, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
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: FunctionalMemory(name), disk(d), console(cons), addr(a)
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{
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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@ -272,7 +272,7 @@ END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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{
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{
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return new AlphaConsole(getInstanceName(), sim_console, disk,
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return new AlphaConsole(getInstanceName(), sim_console, disk,
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system, cpu, clock, num_cpus, mmu, addr);
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system, cpu, clock, num_cpus, addr, mmu);
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}
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}
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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@ -90,10 +90,9 @@ class AlphaConsole : public FunctionalMemory
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public:
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public:
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/** Standard Constructor */
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/** Standard Constructor */
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AlphaConsole(const std::string &name, SimConsole *cons,
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AlphaConsole(const std::string &name, SimConsole *cons,
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SimpleDisk *d, int size,
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SimpleDisk *d, System *system, BaseCPU *cpu,
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System *system, BaseCPU *cpu,
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TsunamiIO *clock, int num_cpus,
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TsunamiIO *clock, int num_cpus,
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Addr addr, Addr mask, MemoryController *mmu);
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Addr a, MemoryController *mmu);
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/**
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/**
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* memory mapped reads and writes
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* memory mapped reads and writes
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@ -20,10 +20,11 @@
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using namespace std;
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using namespace std;
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BadDevice::BadDevice(const string &name,
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BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
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Addr addr, Addr mask, MemoryController *mmu, const string &devicename)
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const string &devicename)
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: MmapDevice(name, addr, mask, mmu), devname(devicename)
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: FunctionalMemory(name), addr(a), devname(devicename)
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{
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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}
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}
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Fault
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Fault
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@ -46,7 +47,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> addr;
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Param<Addr> mask;
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Param<string> devicename;
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Param<string> devicename;
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END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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@ -55,14 +55,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask"),
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INIT_PARAM(devicename, "Name of device to error on")
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INIT_PARAM(devicename, "Name of device to error on")
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END_INIT_SIM_OBJECT_PARAMS(BadDevice)
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END_INIT_SIM_OBJECT_PARAMS(BadDevice)
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CREATE_SIM_OBJECT(BadDevice)
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CREATE_SIM_OBJECT(BadDevice)
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{
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{
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return new BadDevice(getInstanceName(), addr, mask, mmu, devicename);
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return new BadDevice(getInstanceName(), addr, mmu, devicename);
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}
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}
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REGISTER_SIM_OBJECT("BadDevice", BadDevice)
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REGISTER_SIM_OBJECT("BadDevice", BadDevice)
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@ -34,7 +34,7 @@
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#ifndef __BADDEV_HH__
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#ifndef __BADDEV_HH__
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#define __BADDEV_HH__
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#define __BADDEV_HH__
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#include "mem/functional_mem/mmap_device.hh"
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#include "mem/functional_mem/functional_memory.hh"
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/**
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/**
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* BadDevice
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* BadDevice
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@ -42,24 +42,23 @@
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* the user that the kernel they are running has unsupported
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* the user that the kernel they are running has unsupported
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* options (i.e. frame buffer)
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* options (i.e. frame buffer)
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*/
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*/
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class BadDevice : public MmapDevice
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class BadDevice : public FunctionalMemory
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{
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{
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private:
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private:
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Addr addr;
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static const Addr size = 0xf;
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std::string devname;
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std::string devname;
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protected:
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public:
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public:
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/**
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/**
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* The default constructor.
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* The default constructor.
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*/
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*/
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BadDevice(const std::string &name, Addr addr, Addr mask,
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BadDevice(const std::string &name, Addr a, MemoryController *mmu,
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MemoryController *mmu, const std::string &devicename);
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const std::string &devicename);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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};
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};
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#endif // __BADDEV_HH__
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#endif // __BADDEV_HH__
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@ -47,10 +47,12 @@
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using namespace std;
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using namespace std;
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PCIConfigAll::PCIConfigAll(const string &name, Tsunami *t,
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PCIConfigAll::PCIConfigAll(const string &name, Tsunami *t, Addr a,
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Addr addr, Addr mask, MemoryController *mmu)
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MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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: FunctionalMemory(name), addr(a), tsunami(t)
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{
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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// Put back pointer in tsunami
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// Put back pointer in tsunami
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tsunami->pciconfig = this;
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tsunami->pciconfig = this;
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DPRINTF(PCIConfigAll, "read va=%#x size=%d\n",
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DPRINTF(PCIConfigAll, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask);
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Addr daddr = (req->paddr & size);
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int device = (daddr >> 11) & 0x1F;
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int func = (daddr >> 8) & 0x7;
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Fault
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Fault
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PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
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PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
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{
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{
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Addr daddr = (req->paddr & addr_mask);
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Addr daddr = (req->paddr & size);
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int device = (daddr >> 11) & 0x1F;
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int func = (daddr >> 8) & 0x7;
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@ -182,7 +184,7 @@ END_INIT_SIM_OBJECT_PARAMS(PCIConfigAll)
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CREATE_SIM_OBJECT(PCIConfigAll)
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CREATE_SIM_OBJECT(PCIConfigAll)
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{
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{
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return new PCIConfigAll(getInstanceName(), tsunami, addr, mask, mmu);
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return new PCIConfigAll(getInstanceName(), tsunami, addr, mmu);
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}
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}
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REGISTER_SIM_OBJECT("PCIConfigAll", PCIConfigAll)
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REGISTER_SIM_OBJECT("PCIConfigAll", PCIConfigAll)
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@ -38,7 +38,7 @@
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#ifndef __PCICONFIGALL_HH__
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#ifndef __PCICONFIGALL_HH__
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#define __PCICONFIGALL_HH__
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#define __PCICONFIGALL_HH__
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#include "mem/functional_mem/mmap_device.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "dev/tsunami.hh"
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#include "dev/tsunami.hh"
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#include "dev/pcireg.h"
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#include "dev/pcireg.h"
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@ -54,9 +54,11 @@ class PciDev;
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* space and passes the requests on to TsunamiPCIDev devices as
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* space and passes the requests on to TsunamiPCIDev devices as
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* appropriate.
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* appropriate.
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*/
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*/
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class PCIConfigAll : public MmapDevice
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class PCIConfigAll : public FunctionalMemory
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{
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{
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private:
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private:
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Addr addr;
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static const Addr size = 0xffffff;
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protected:
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protected:
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/**
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/**
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* The default constructor.
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* The default constructor.
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*/
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*/
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PCIConfigAll(const std::string &name, Tsunami *t,
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PCIConfigAll(const std::string &name, Tsunami *t, Addr a,
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Addr addr, Addr mask, MemoryController *mmu);
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MemoryController *mmu);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
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PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
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PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
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PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
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: MmapDevice(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
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: FunctionalMemory(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
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Bus(bus), Device(dev), Function(func)
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Bus(bus), Device(dev), Function(func)
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{
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{
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// copy the config data from the PciConfigData object
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// copy the config data from the PciConfigData object
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(config.data[offset] & 0x3);
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(config.data[offset] & 0x3);
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if (word_value & ~0x1) {
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if (word_value & ~0x1) {
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Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
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Addr base_size = BARSize[barnum]-1;
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// It's never been set
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// It's never been set
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if (BARAddrs[barnum] == 0)
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if (BARAddrs[barnum] == 0)
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AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO,
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MMU->add_child(this,
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BARSize[barnum]-1, MMU);
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Range<Addr>(base_addr,
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base_addr + base_size));
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else
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else
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ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
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MMU->update_child(this,
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(word_value & ~0x1) + TSUNAMI_PCI0_IO,
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Range<Addr>(BARAddrs[barnum],
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BARSize[barnum]-1, MMU);
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BARAddrs[barnum] +
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BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
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base_size),
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Range<Addr>(base_addr,
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base_addr +
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base_size));
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BARAddrs[barnum] = base_addr;
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}
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}
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} else {
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} else {
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@ -197,17 +206,26 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
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(config.data[offset] & 0xF);
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(config.data[offset] & 0xF);
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if (word_value & ~0x3) {
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if (word_value & ~0x3) {
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Addr base_addr = (word_value & ~0x3) +
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TSUNAMI_PCI0_MEMORY;
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Addr base_size = BARSize[barnum]-1;
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// It's never been set
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// It's never been set
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if (BARAddrs[barnum] == 0)
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if (BARAddrs[barnum] == 0)
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AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY,
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MMU->add_child(this,
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BARSize[barnum]-1, MMU);
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Range<Addr>(base_addr,
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base_addr + base_size));
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else
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else
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ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
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MMU->update_child(this,
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(word_value & ~0x3) +
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Range<Addr>(BARAddrs[barnum],
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TSUNAMI_PCI0_MEMORY,
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BARAddrs[barnum] +
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BARSize[barnum]-1, MMU);
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base_size),
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BARAddrs[barnum] = (word_value & ~0x3) +
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Range<Addr>(base_addr,
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TSUNAMI_PCI0_MEMORY;
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base_addr +
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base_size));
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BARAddrs[barnum] = base_addr;
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}
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}
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}
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}
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}
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}
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@ -35,7 +35,7 @@
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#include "dev/pcireg.h"
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#include "dev/pcireg.h"
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#include "sim/sim_object.hh"
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#include "sim/sim_object.hh"
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#include "mem/functional_mem/mmap_device.hh"
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#include "mem/functional_mem/functional_memory.hh"
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class PCIConfigAll;
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class PCIConfigAll;
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class MemoryController;
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class MemoryController;
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@ -63,7 +63,7 @@ class PciConfigData : public SimObject
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* register with it. This object registers with the PCIConfig space
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* register with it. This object registers with the PCIConfig space
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* object.
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* object.
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*/
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*/
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class PciDev : public MmapDevice
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class PciDev : public FunctionalMemory
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{
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{
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protected:
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protected:
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MemoryController *MMU;
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MemoryController *MMU;
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@ -21,10 +21,12 @@
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using namespace std;
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
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Addr addr, Addr mask, MemoryController *mmu)
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MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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: FunctionalMemory(name), addr(a), tsunami(t)
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{
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dim[i] = 0;
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dim[i] = 0;
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dir[i] = 0;
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dir[i] = 0;
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@ -45,7 +47,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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Addr daddr = (req->paddr & size) >> 6;
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ExecContext *xc = req->xc;
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ExecContext *xc = req->xc;
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|
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switch (req->size) {
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switch (req->size) {
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|
@ -131,7 +133,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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req->vaddr, req->size);
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|
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Addr daddr = (req->paddr & addr_mask) >> 6;
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Addr daddr = (req->paddr & size) >> 6;
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|
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switch (req->size) {
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switch (req->size) {
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|
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|
@ -291,7 +293,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
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SimObjectParam<Tsunami *> tsunami;
|
SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> addr;
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Param<Addr> mask;
|
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
|
@ -299,14 +300,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
INIT_PARAM(tsunami, "Tsunami"),
|
INIT_PARAM(tsunami, "Tsunami"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address")
|
||||||
INIT_PARAM(mask, "Address Mask")
|
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiCChip)
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
||||||
{
|
{
|
||||||
return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
|
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|
||||||
|
|
|
@ -33,15 +33,17 @@
|
||||||
#ifndef __TSUNAMI_CCHIP_HH__
|
#ifndef __TSUNAMI_CCHIP_HH__
|
||||||
#define __TSUNAMI_CCHIP_HH__
|
#define __TSUNAMI_CCHIP_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/mmap_device.hh"
|
#include "mem/functional_mem/functional_memory.hh"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami CChip
|
* Tsunami CChip
|
||||||
*/
|
*/
|
||||||
class TsunamiCChip : public MmapDevice
|
class TsunamiCChip : public FunctionalMemory
|
||||||
{
|
{
|
||||||
public:
|
private:
|
||||||
|
Addr addr;
|
||||||
|
static const Addr size = 0xfff;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
/**
|
/**
|
||||||
|
@ -71,8 +73,8 @@ class TsunamiCChip : public MmapDevice
|
||||||
uint64_t drir;
|
uint64_t drir;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
TsunamiCChip(const std::string &name, Tsunami *t,
|
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
|
||||||
Addr addr, Addr mask, MemoryController *mmu);
|
MemoryController *mmu);
|
||||||
|
|
||||||
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
|
|
@ -125,9 +125,11 @@ TsunamiIO::ClockEvent::Status()
|
||||||
}
|
}
|
||||||
|
|
||||||
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
|
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
|
||||||
Addr addr, Addr mask, MemoryController *mmu)
|
Addr a, MemoryController *mmu)
|
||||||
: MmapDevice(name, addr, mask, mmu), tsunami(t), rtc(t)
|
: FunctionalMemory(name), addr(a), tsunami(t), rtc(t)
|
||||||
{
|
{
|
||||||
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
// set the back pointer from tsunami to myself
|
// set the back pointer from tsunami to myself
|
||||||
tsunami->io = this;
|
tsunami->io = this;
|
||||||
|
|
||||||
|
@ -151,7 +153,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
|
||||||
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
|
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
|
||||||
req->vaddr, req->size, req->vaddr & 0xfff);
|
req->vaddr, req->size, req->vaddr & 0xfff);
|
||||||
|
|
||||||
Addr daddr = (req->paddr & addr_mask);
|
Addr daddr = (req->paddr & size);
|
||||||
// ExecContext *xc = req->xc;
|
// ExecContext *xc = req->xc;
|
||||||
// int cpuid = xc->cpu_id;
|
// int cpuid = xc->cpu_id;
|
||||||
|
|
||||||
|
@ -226,7 +228,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
|
||||||
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
|
||||||
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
req->vaddr, req->size, req->vaddr & 0xfff, dt64);
|
||||||
|
|
||||||
Addr daddr = (req->paddr & addr_mask);
|
Addr daddr = (req->paddr & size);
|
||||||
|
|
||||||
switch(req->size) {
|
switch(req->size) {
|
||||||
case sizeof(uint8_t):
|
case sizeof(uint8_t):
|
||||||
|
@ -359,7 +361,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
Param<time_t> time;
|
Param<time_t> time;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
Param<Addr> mask;
|
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
|
|
||||||
|
@ -369,15 +370,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
INIT_PARAM_DFLT(time, "System time to use "
|
INIT_PARAM_DFLT(time, "System time to use "
|
||||||
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
|
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address")
|
||||||
INIT_PARAM(mask, "Address Mask")
|
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiIO)
|
CREATE_SIM_OBJECT(TsunamiIO)
|
||||||
{
|
{
|
||||||
return new TsunamiIO(getInstanceName(), tsunami, time, addr,
|
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu);
|
||||||
mask, mmu);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
|
||||||
|
|
|
@ -35,16 +35,18 @@
|
||||||
|
|
||||||
#define RTC_RATE 1024
|
#define RTC_RATE 1024
|
||||||
|
|
||||||
#include "mem/functional_mem/mmap_device.hh"
|
#include "mem/functional_mem/functional_memory.hh"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami I/O device
|
* Tsunami I/O device
|
||||||
*/
|
*/
|
||||||
class TsunamiIO : public MmapDevice
|
class TsunamiIO : public FunctionalMemory
|
||||||
{
|
{
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
Addr addr;
|
||||||
|
static const Addr size = 0xff;
|
||||||
|
|
||||||
struct tm tm;
|
struct tm tm;
|
||||||
|
|
||||||
// In Tsunami RTC only has two i/o ports
|
// In Tsunami RTC only has two i/o ports
|
||||||
|
@ -121,7 +123,7 @@ class TsunamiIO : public MmapDevice
|
||||||
uint32_t frequency() const { return RTC_RATE; }
|
uint32_t frequency() const { return RTC_RATE; }
|
||||||
|
|
||||||
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
|
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
|
||||||
Addr addr, Addr mask, MemoryController *mmu);
|
Addr a, MemoryController *mmu);
|
||||||
|
|
||||||
void set_time(time_t t);
|
void set_time(time_t t);
|
||||||
|
|
||||||
|
|
|
@ -23,10 +23,12 @@
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t,
|
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
|
||||||
Addr addr, Addr mask, MemoryController *mmu)
|
MemoryController *mmu)
|
||||||
: MmapDevice(name, addr, mask, mmu), tsunami(t)
|
: FunctionalMemory(name), addr(a), tsunami(t)
|
||||||
{
|
{
|
||||||
|
mmu->add_child(this, Range<Addr>(addr, addr + size));
|
||||||
|
|
||||||
wsba0 = 0;
|
wsba0 = 0;
|
||||||
wsba1 = 0;
|
wsba1 = 0;
|
||||||
wsba2 = 0;
|
wsba2 = 0;
|
||||||
|
@ -50,7 +52,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
|
||||||
DPRINTF(Tsunami, "read va=%#x size=%d\n",
|
DPRINTF(Tsunami, "read va=%#x size=%d\n",
|
||||||
req->vaddr, req->size);
|
req->vaddr, req->size);
|
||||||
|
|
||||||
Addr daddr = (req->paddr & addr_mask) >> 6;
|
Addr daddr = (req->paddr & size) >> 6;
|
||||||
// ExecContext *xc = req->xc;
|
// ExecContext *xc = req->xc;
|
||||||
// int cpuid = xc->cpu_id;
|
// int cpuid = xc->cpu_id;
|
||||||
|
|
||||||
|
@ -140,7 +142,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
|
||||||
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
|
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
|
||||||
req->vaddr, req->size);
|
req->vaddr, req->size);
|
||||||
|
|
||||||
Addr daddr = (req->paddr & addr_mask) >> 6;
|
Addr daddr = (req->paddr & size) >> 6;
|
||||||
|
|
||||||
switch (req->size) {
|
switch (req->size) {
|
||||||
|
|
||||||
|
@ -239,7 +241,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
SimObjectParam<Tsunami *> tsunami;
|
SimObjectParam<Tsunami *> tsunami;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
Param<Addr> mask;
|
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
|
@ -247,14 +248,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
INIT_PARAM(tsunami, "Tsunami"),
|
INIT_PARAM(tsunami, "Tsunami"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address")
|
||||||
INIT_PARAM(mask, "Address Mask")
|
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiPChip)
|
CREATE_SIM_OBJECT(TsunamiPChip)
|
||||||
{
|
{
|
||||||
return new TsunamiPChip(getInstanceName(), tsunami, addr, mask, mmu);
|
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
|
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
|
||||||
|
|
|
@ -33,15 +33,17 @@
|
||||||
#ifndef __TSUNAMI_PCHIP_HH__
|
#ifndef __TSUNAMI_PCHIP_HH__
|
||||||
#define __TSUNAMI_PCHIP_HH__
|
#define __TSUNAMI_PCHIP_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/mmap_device.hh"
|
#include "mem/functional_mem/functional_memory.hh"
|
||||||
#include "dev/tsunami.hh"
|
#include "dev/tsunami.hh"
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami PChip
|
* Tsunami PChip
|
||||||
*/
|
*/
|
||||||
class TsunamiPChip : public MmapDevice
|
class TsunamiPChip : public FunctionalMemory
|
||||||
{
|
{
|
||||||
public:
|
private:
|
||||||
|
Addr addr;
|
||||||
|
static const Addr size = 0xfff;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
Tsunami *tsunami;
|
Tsunami *tsunami;
|
||||||
|
@ -61,8 +63,8 @@ class TsunamiPChip : public MmapDevice
|
||||||
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
TsunamiPChip(const std::string &name, Tsunami *t,
|
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
|
||||||
Addr addr, Addr mask, MemoryController *mmu);
|
MemoryController *mmu);
|
||||||
|
|
||||||
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
|
|
@ -31,10 +31,10 @@ using namespace std;
|
||||||
#define CONS_INT_TX 0x01 // interrupt enable / state bits
|
#define CONS_INT_TX 0x01 // interrupt enable / state bits
|
||||||
#define CONS_INT_RX 0x02
|
#define CONS_INT_RX 0x02
|
||||||
|
|
||||||
TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
|
TsunamiUart::TsunamiUart(const string &name, SimConsole *c, Addr a,
|
||||||
Addr addr, Addr mask, MemoryController *mmu)
|
MemoryController *mmu)
|
||||||
: MmapDevice(name, addr, mask, mmu),
|
: FunctionalMemory(name), addr(a), cons(c), status_store(0),
|
||||||
cons(c), status_store(0), valid_char(false)
|
valid_char(false)
|
||||||
{
|
{
|
||||||
IER = 0;
|
IER = 0;
|
||||||
}
|
}
|
||||||
|
@ -42,7 +42,7 @@ TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
|
||||||
Fault
|
Fault
|
||||||
TsunamiUart::read(MemReqPtr &req, uint8_t *data)
|
TsunamiUart::read(MemReqPtr &req, uint8_t *data)
|
||||||
{
|
{
|
||||||
Addr daddr = req->paddr & addr_mask;
|
Addr daddr = req->paddr & size;
|
||||||
DPRINTF(TsunamiUart, " read register %#x\n", daddr);
|
DPRINTF(TsunamiUart, " read register %#x\n", daddr);
|
||||||
|
|
||||||
switch (req->size) {
|
switch (req->size) {
|
||||||
|
@ -130,7 +130,7 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data)
|
||||||
Fault
|
Fault
|
||||||
TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
|
TsunamiUart::write(MemReqPtr &req, const uint8_t *data)
|
||||||
{
|
{
|
||||||
Addr daddr = req->paddr & addr_mask;
|
Addr daddr = req->paddr & size;
|
||||||
|
|
||||||
DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
|
||||||
switch (daddr) {
|
switch (daddr) {
|
||||||
|
@ -198,7 +198,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
SimObjectParam<SimConsole *> console;
|
SimObjectParam<SimConsole *> console;
|
||||||
SimObjectParam<MemoryController *> mmu;
|
SimObjectParam<MemoryController *> mmu;
|
||||||
Param<Addr> addr;
|
Param<Addr> addr;
|
||||||
Param<Addr> mask;
|
|
||||||
|
|
||||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
|
@ -206,14 +205,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
INIT_PARAM(console, "The console"),
|
INIT_PARAM(console, "The console"),
|
||||||
INIT_PARAM(mmu, "Memory Controller"),
|
INIT_PARAM(mmu, "Memory Controller"),
|
||||||
INIT_PARAM(addr, "Device Address"),
|
INIT_PARAM(addr, "Device Address")
|
||||||
INIT_PARAM(mask, "Address Mask")
|
|
||||||
|
|
||||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiUart)
|
||||||
|
|
||||||
CREATE_SIM_OBJECT(TsunamiUart)
|
CREATE_SIM_OBJECT(TsunamiUart)
|
||||||
{
|
{
|
||||||
return new TsunamiUart(getInstanceName(), console, addr, mask, mmu);
|
return new TsunamiUart(getInstanceName(), console, addr, mmu);
|
||||||
}
|
}
|
||||||
|
|
||||||
REGISTER_SIM_OBJECT("TsunamiUart", TsunamiUart)
|
REGISTER_SIM_OBJECT("TsunamiUart", TsunamiUart)
|
||||||
|
|
|
@ -33,15 +33,19 @@
|
||||||
#ifndef __TSUNAMI_UART_HH__
|
#ifndef __TSUNAMI_UART_HH__
|
||||||
#define __TSUNAMI_UART_HH__
|
#define __TSUNAMI_UART_HH__
|
||||||
|
|
||||||
#include "mem/functional_mem/mmap_device.hh"
|
#include "mem/functional_mem/functional_memory.hh"
|
||||||
|
|
||||||
class SimConsole;
|
class SimConsole;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tsunami UART
|
* Tsunami UART
|
||||||
*/
|
*/
|
||||||
class TsunamiUart : public MmapDevice
|
class TsunamiUart : public FunctionalMemory
|
||||||
{
|
{
|
||||||
|
private:
|
||||||
|
Addr addr;
|
||||||
|
static const Addr size = 0xf;
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
SimConsole *cons;
|
SimConsole *cons;
|
||||||
int status_store;
|
int status_store;
|
||||||
|
@ -50,8 +54,8 @@ class TsunamiUart : public MmapDevice
|
||||||
uint8_t IER;
|
uint8_t IER;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
TsunamiUart(const std::string &name, SimConsole *c,
|
TsunamiUart(const std::string &name, SimConsole *c, Addr a,
|
||||||
Addr addr, Addr mask, MemoryController *mmu);
|
MemoryController *mmu);
|
||||||
|
|
||||||
Fault read(MemReqPtr &req, uint8_t *data);
|
Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
Fault write(MemReqPtr &req, const uint8_t *data);
|
Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
|
Loading…
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