arm: Create a GIC base class and make the PL390 derive from it

This patch moves the GIC interface to a separate base class and makes
all interrupt devices use that base class instead of a pointer to the
PL390 implementation. This allows us to have multiple GIC
implementations. Future implementations will allow in-kernel GIC
implementations when using hardware virtualization.

--HG--
rename : src/dev/arm/gic.cc => src/dev/arm/gic_pl390.cc
rename : src/dev/arm/gic.hh => src/dev/arm/gic_pl390.hh

src/dev/arm/Gic.py

@@ -0,0 +1,61 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import *
+
+from Device import PioDevice
+from Platform import Platform
+
+class BaseGic(PioDevice):
+    type = 'BaseGic'
+    abstract = True
+    cxx_header = "dev/arm/base_gic.hh"
+
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
+
+class Pl390(BaseGic):
+    type = 'Pl390'
+    cxx_header = "dev/arm/gic_pl390.hh"
+
+    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
+    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
+    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
+    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
+    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
+    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
+

src/dev/arm/RealView.py

@@ -50,6 +50,7 @@ from Platform import Platform
 from Terminal import Terminal
 from Uart import Uart
 from SimpleMemory import SimpleMemory
+from Gic import *
 
 class AmbaDevice(BasicPioDevice):
     type = 'AmbaDevice'
@@ -61,7 +62,7 @@ class AmbaIntDevice(AmbaDevice):
     type = 'AmbaIntDevice'
     abstract = True
     cxx_header = "dev/arm/amba_device.hh"
-    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num = Param.UInt32("Interrupt number that connects to GIC")
     int_delay = Param.Latency("100ns",
             "Time between action and interrupt generation by device")
@@ -72,7 +73,7 @@ class AmbaDmaDevice(DmaDevice):
     cxx_header = "dev/arm/amba_device.hh"
     pio_addr = Param.Addr("Address for AMBA slave interface")
     pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
-    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num = Param.UInt32("Interrupt number that connects to GIC")
     amba_id = Param.UInt32("ID of AMBA device for kernel detection")
 
@@ -87,17 +88,6 @@ class RealViewCtrl(BasicPioDevice):
     proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
     idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
 
-class Gic(PioDevice):
-    type = 'Gic'
-    cxx_header = "dev/arm/gic.hh"
-    platform = Param.Platform(Parent.any, "Platform this device is part of.")
-    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
-    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
-    dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
-    cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
-    int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
-    it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
-
 class AmbaFake(AmbaDevice):
     type = 'AmbaFake'
     cxx_header = "dev/arm/amba_fake.hh"
@@ -107,7 +97,7 @@ class AmbaFake(AmbaDevice):
 class Pl011(Uart):
     type = 'Pl011'
     cxx_header = "dev/arm/pl011.hh"
-    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num = Param.UInt32("Interrupt number that connects to GIC")
     end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
     int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
@@ -115,7 +105,7 @@ class Pl011(Uart):
 class Sp804(AmbaDevice):
     type = 'Sp804'
     cxx_header = "dev/arm/timer_sp804.hh"
-    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num0 = Param.UInt32("Interrupt number that connects to GIC")
     clock0 = Param.Clock('1MHz', "Clock speed of the input")
     int_num1 = Param.UInt32("Interrupt number that connects to GIC")
@@ -125,7 +115,7 @@ class Sp804(AmbaDevice):
 class CpuLocalTimer(BasicPioDevice):
     type = 'CpuLocalTimer'
     cxx_header = "dev/arm/timer_cpulocal.hh"
-    gic = Param.Gic(Parent.any, "Gic to use for interrupting")
+    gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
     int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
     # Override the default clock
@@ -174,7 +164,7 @@ class RealView(Platform):
 class RealViewPBX(RealView):
     uart = Pl011(pio_addr=0x10009000, int_num=44)
     realview_io = RealViewCtrl(pio_addr=0x10000000)
-    gic = Gic()
+    gic = Pl390()
     timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
     timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
     local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600)
@@ -262,7 +252,7 @@ class RealViewPBX(RealView):
 class RealViewEB(RealView):
     uart = Pl011(pio_addr=0x10009000, int_num=44)
     realview_io = RealViewCtrl(pio_addr=0x10000000)
-    gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000)
+    gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
     timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
     timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
     clcd   = Pl111(pio_addr=0x10020000, int_num=23)
@@ -338,7 +328,7 @@ class VExpress_EMM(RealView):
     pci_cfg_base = 0x30000000
     uart = Pl011(pio_addr=0x1c090000, int_num=37)
     realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
-    gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
+    gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
     local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000)
     timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
     timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')

src/dev/arm/SConscript

@@ -40,12 +40,14 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'arm':
+    SimObject('Gic.py')
     SimObject('RealView.py')
 
     Source('a9scu.cc')
     Source('amba_device.cc')
     Source('amba_fake.cc')
-    Source('gic.cc')
+    Source('base_gic.cc')
+    Source('gic_pl390.cc')
     Source('pl011.cc')
     Source('pl111.cc')
     Source('kmi.cc')

src/dev/arm/amba_device.hh

@@ -49,7 +49,7 @@
 #ifndef __DEV_ARM_AMBA_DEVICE_HH__
 #define __DEV_ARM_AMBA_DEVICE_HH__
 
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/dma_device.hh"
 #include "dev/io_device.hh"
 #include "mem/packet.hh"
@@ -86,7 +86,7 @@ class AmbaIntDevice : public AmbaDevice
 {
   protected:
     int intNum;
-    Gic *gic;
+    BaseGic *gic;
     Tick intDelay;
 
   public:
@@ -102,7 +102,7 @@ class AmbaDmaDevice : public DmaDevice
     Addr     pioSize;
     Tick     pioDelay;
     int      intNum;
-    Gic      *gic;
+    BaseGic  *gic;
 
   public:
     typedef AmbaDmaDeviceParams Params;

src/dev/arm/base_gic.cc

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "dev/arm/base_gic.hh"
+
+#include "params/BaseGic.hh"
+
+BaseGic::BaseGic(const Params *p)
+        : PioDevice(p),
+          platform(p->platform)
+{
+}
+
+BaseGic::~BaseGic()
+{
+}
+
+const BaseGic::Params *
+BaseGic::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}

src/dev/arm/base_gic.hh

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+/** @file
+ * Base class for ARM GIC implementations
+ */
+
+#ifndef __DEV_ARM_BASE_GIC_H__
+#define __DEV_ARM_BASE_GIC_H__
+
+#include "dev/io_device.hh"
+
+class Platform;
+
+class BaseGic :  public PioDevice
+{
+  public:
+    typedef struct BaseGicParams Params;
+
+    BaseGic(const Params *p);
+    virtual ~BaseGic();
+
+    const Params * params() const;
+
+    /**
+     * Post an interrupt from a device that is connected to the GIC.
+     *
+     * Depending on the configuration, the GIC will pass this interrupt
+     * on through to a CPU.
+     *
+     * @param num number of interrupt to send
+     */
+    virtual void sendInt(uint32_t num) = 0;
+
+    /**
+     * Interface call for private peripheral interrupts.
+     *
+     * @param num number of interrupt to send
+     * @param cpu CPU to forward interrupt to
+     */
+    virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
+
+    /**
+     * Clear an interrupt from a device that is connected to the GIC.
+     *
+     * Depending on the configuration, the GIC may de-assert it's CPU
+     * line.
+     *
+     * @param num number of interrupt to send
+     */
+    virtual void clearInt(uint32_t num) = 0;
+
+  protected:
+    /** Platform this GIC belongs to. */
+    Platform *platform;
+};
+
+#endif

src/dev/arm/gic_pl390.cc

@@ -46,14 +46,14 @@
 #include "debug/GIC.hh"
 #include "debug/IPI.hh"
 #include "debug/Interrupt.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/gic_pl390.hh"
 #include "dev/arm/realview.hh"
 #include "dev/terminal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 
-Gic::Gic(const Params *p)
-    : PioDevice(p), platform(p->platform), distAddr(p->dist_addr),
+Pl390::Pl390(const Params *p)
+    : BaseGic(p), distAddr(p->dist_addr),
       cpuAddr(p->cpu_addr), distPioDelay(p->dist_pio_delay),
       cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
       enabled(false), itLines(p->it_lines)
@@ -108,7 +108,7 @@ Gic::Gic(const Params *p)
 }
 
 Tick
-Gic::read(PacketPtr pkt)
+Pl390::read(PacketPtr pkt)
 {
 
     Addr addr = pkt->getAddr();
@@ -123,7 +123,7 @@ Gic::read(PacketPtr pkt)
 
 
 Tick
-Gic::write(PacketPtr pkt)
+Pl390::write(PacketPtr pkt)
 {
 
     Addr addr = pkt->getAddr();
@@ -137,7 +137,7 @@ Gic::write(PacketPtr pkt)
 }
 
 Tick
-Gic::readDistributor(PacketPtr pkt)
+Pl390::readDistributor(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - distAddr;
     pkt->allocate();
@@ -267,7 +267,7 @@ done:
 }
 
 Tick
-Gic::readCpu(PacketPtr pkt)
+Pl390::readCpu(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - cpuAddr;
     pkt->allocate();
@@ -353,7 +353,7 @@ Gic::readCpu(PacketPtr pkt)
 
 
 Tick
-Gic::writeDistributor(PacketPtr pkt)
+Pl390::writeDistributor(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - distAddr;
     pkt->allocate();
@@ -477,7 +477,7 @@ done:
 }
 
 Tick
-Gic::writeCpu(PacketPtr pkt)
+Pl390::writeCpu(PacketPtr pkt)
 {
     Addr daddr = pkt->getAddr() - cpuAddr;
     pkt->allocate();
@@ -532,7 +532,7 @@ Gic::writeCpu(PacketPtr pkt)
 }
 
 void
-Gic::softInt(int ctx_id, SWI swi)
+Pl390::softInt(int ctx_id, SWI swi)
 {
     switch (swi.list_type) {
       case 1:
@@ -564,7 +564,7 @@ Gic::softInt(int ctx_id, SWI swi)
 }
 
 uint64_t
-Gic::genSwiMask(int cpu)
+Pl390::genSwiMask(int cpu)
 {
     if (cpu > 7)
         panic("Invalid CPU ID\n");
@@ -572,7 +572,7 @@ Gic::genSwiMask(int cpu)
 }
 
 void
-Gic::updateIntState(int hint)
+Pl390::updateIntState(int hint)
 {
     for (int cpu = 0; cpu < CPU_MAX; cpu++) {
         if (!cpuEnabled[cpu])
@@ -647,7 +647,7 @@ Gic::updateIntState(int hint)
 }
 
 void
-Gic::updateRunPri()
+Pl390::updateRunPri()
 {
     for (int cpu = 0; cpu < CPU_MAX; cpu++) {
         if (!cpuEnabled[cpu])
@@ -674,7 +674,7 @@ Gic::updateRunPri()
 }
 
 void
-Gic::sendInt(uint32_t num)
+Pl390::sendInt(uint32_t num)
 {
     DPRINTF(Interrupt, "Received Interupt number %d,  cpuTarget %#x: \n",
             num, cpuTarget[num]);
@@ -686,7 +686,7 @@ Gic::sendInt(uint32_t num)
 }
 
 void
-Gic::sendPPInt(uint32_t num, uint32_t cpu)
+Pl390::sendPPInt(uint32_t num, uint32_t cpu)
 {
     DPRINTF(Interrupt, "Received Interrupt number %d, cpuTarget %#x: \n",
             num, cpu);
@@ -695,20 +695,20 @@ Gic::sendPPInt(uint32_t num, uint32_t cpu)
 }
 
 void
-Gic::clearInt(uint32_t number)
+Pl390::clearInt(uint32_t number)
 {
     /* @todo assume edge triggered only at the moment. Nothing to do. */
 }
 
 void
-Gic::postInt(uint32_t cpu, Tick when)
+Pl390::postInt(uint32_t cpu, Tick when)
 {
     if (!(postIntEvent[cpu]->scheduled()))
         eventq->schedule(postIntEvent[cpu], when);
 }
 
 AddrRangeList
-Gic::getAddrRanges() const
+Pl390::getAddrRanges() const
 {
     AddrRangeList ranges;
     ranges.push_back(RangeSize(distAddr, DIST_SIZE));
@@ -718,7 +718,7 @@ Gic::getAddrRanges() const
 
 
 void
-Gic::serialize(std::ostream &os)
+Pl390::serialize(std::ostream &os)
 {
     DPRINTF(Checkpoint, "Serializing Arm GIC\n");
 
@@ -758,7 +758,7 @@ Gic::serialize(std::ostream &os)
 }
 
 void
-Gic::unserialize(Checkpoint *cp, const std::string &section)
+Pl390::unserialize(Checkpoint *cp, const std::string &section)
 {
     DPRINTF(Checkpoint, "Unserializing Arm GIC\n");
 
@@ -797,15 +797,15 @@ Gic::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-Gic *
-GicParams::create()
+Pl390 *
+Pl390Params::create()
 {
-    return new Gic(this);
+    return new Pl390(this);
 }
 
 /* Functions for debugging and testing */
 void
-Gic::driveSPI(unsigned int spiVect)
+Pl390::driveSPI(unsigned int spiVect)
 {
     DPRINTF(GIC, "Received SPI Vector:%x Enable: %d\n", spiVect, irqEnable);
     pendingInt[1] |= spiVect;
@@ -815,7 +815,7 @@ Gic::driveSPI(unsigned int spiVect)
 }
 
 void
-Gic::driveIrqEn( bool state)
+Pl390::driveIrqEn( bool state)
 {
     irqEnable = state;
     DPRINTF(GIC, " Enabling Irq\n");
@@ -823,7 +823,7 @@ Gic::driveIrqEn( bool state)
 }
 
 void
-Gic::driveLegIRQ(bool state)
+Pl390::driveLegIRQ(bool state)
 {
     if (irqEnable && !(!enabled && cpuEnabled[0])) {
         if (state) {
@@ -835,7 +835,7 @@ Gic::driveLegIRQ(bool state)
 }
 
 void
-Gic::driveLegFIQ(bool state)
+Pl390::driveLegFIQ(bool state)
 {
     if (state)
         platform->intrctrl->post(0, ArmISA::INT_FIQ, 0);

src/dev/arm/gic_pl390.hh

@@ -45,14 +45,15 @@
  * Implementiation of a PL390 GIC
  */
 
-#ifndef __DEV_ARM_GIC_H__
-#define __DEV_ARM_GIC_H__
+#ifndef __DEV_ARM_GIC_PL390_H__
+#define __DEV_ARM_GIC_PL390_H__
 
 #include "base/bitunion.hh"
+#include "cpu/intr_control.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/io_device.hh"
 #include "dev/platform.hh"
-#include "cpu/intr_control.hh"
-#include "params/Gic.hh"
+#include "params/Pl390.hh"
 
 /** @todo this code only assumes one processor for now. Low word
  * of intEnabled and pendingInt need to be replicated per CPU.
@@ -60,7 +61,7 @@
  * for interrupt priority register, processor target registers
  * interrupt config registers  */
 
-class Gic : public PioDevice
+class Pl390 : public BaseGic
 {
   protected:
     // distributor memory addresses
@@ -123,8 +124,6 @@ class Gic : public PioDevice
         Bitfield<12,10> cpu_id;
     EndBitUnion(IAR)
 
-    Platform *platform;
-
     /** Distributor address GIC listens at */
     Addr distAddr;
 
@@ -249,13 +248,13 @@ class Gic : public PioDevice
     PostIntEvent *postIntEvent[CPU_MAX];
 
   public:
-   typedef GicParams Params;
-   const Params *
+    typedef Pl390Params Params;
+    const Params *
     params() const
     {
         return dynamic_cast<const Params *>(_params);
     }
-    Gic(const Params *p);
+    Pl390(const Params *p);
 
     /** Return the address ranges used by the Gic
      * This is the distributor address + all cpu addresses

src/dev/arm/kmi.hh

@@ -54,8 +54,6 @@
 #include "dev/arm/amba_device.hh"
 #include "params/Pl050.hh"
 
-class Gic;
-
 class Pl050 : public AmbaIntDevice, public VncKeyboard, public VncMouse
 {
   protected:

src/dev/arm/pl011.cc

@@ -44,7 +44,7 @@
 #include "debug/Checkpoint.hh"
 #include "debug/Uart.hh"
 #include "dev/arm/amba_device.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/arm/pl011.hh"
 #include "dev/terminal.hh"
 #include "mem/packet.hh"

src/dev/arm/pl011.hh

@@ -54,7 +54,7 @@
 #include "dev/uart.hh"
 #include "params/Pl011.hh"
 
-class Gic;
+class BaseGic;
 
 class Pl011 : public Uart
 {
@@ -121,7 +121,7 @@ class Pl011 : public Uart
     int intNum;
 
     /** Gic to use for interrupting */
-    Gic *gic;
+    BaseGic *gic;
 
     /** Should the simulation end on an EOT */
     bool endOnEOT;

src/dev/arm/pl111.cc

@@ -45,10 +45,11 @@
 #include "debug/PL111.hh"
 #include "debug/Uart.hh"
 #include "dev/arm/amba_device.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/arm/pl111.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/system.hh"
 
 // clang complains about std::set being overloaded with Packet::set if
 // we open up the entire namespace std

src/dev/arm/pl111.hh

@@ -52,7 +52,6 @@
 #include "params/Pl111.hh"
 #include "sim/serialize.hh"
 
-class Gic;
 class VncInput;
 class Bitmap;
 

src/dev/arm/realview.cc

@@ -50,7 +50,7 @@
 
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/arm/realview.hh"
 #include "dev/terminal.hh"
 #include "sim/system.hh"

src/dev/arm/realview.hh

@@ -52,7 +52,7 @@
 #include "dev/platform.hh"
 #include "params/RealView.hh"
 
-class Gic;
+class BaseGic;
 class IdeController;
 class System;
 
@@ -62,7 +62,7 @@ class RealView : public Platform
     /** Pointer to the system */
     System *system;
 
-    Gic *gic;
+    BaseGic *gic;
 
   public:
     typedef RealViewParams Params;
@@ -80,7 +80,7 @@ class RealView : public Platform
     RealView(const Params *p);
 
     /** Give platform a pointer to interrupt controller */
-    void setGic(Gic *_gic) { gic = _gic; }
+    void setGic(BaseGic *_gic) { gic = _gic; }
 
     /**
      * Cause the cpu to post a serial interrupt to the CPU.

src/dev/arm/timer_cpulocal.cc

@@ -42,7 +42,7 @@
 #include "base/trace.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/Timer.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/arm/timer_cpulocal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

src/dev/arm/timer_cpulocal.hh

@@ -50,7 +50,7 @@
  * Technical Reference Manual rev r2p2 (ARM DDI 0407F)
  */
 
-class Gic;
+class BaseGic;
 
 class CpuLocalTimer : public BasicPioDevice
 {
@@ -157,7 +157,7 @@ class CpuLocalTimer : public BasicPioDevice
     static const int CPU_MAX = 8;
 
     /** Pointer to the GIC for causing an interrupt */
-    Gic *gic;
+    BaseGic *gic;
 
     /** Timers that do the actual work */
     Timer localTimer[CPU_MAX];

src/dev/arm/timer_sp804.cc

@@ -41,7 +41,7 @@
 #include "base/trace.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/Timer.hh"
-#include "dev/arm/gic.hh"
+#include "dev/arm/base_gic.hh"
 #include "dev/arm/timer_sp804.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

src/dev/arm/timer_sp804.hh

@@ -47,7 +47,7 @@
  * This implements the dual Sp804 timer block
  */
 
-class Gic;
+class BaseGic;
 
 class Sp804 : public AmbaDevice
 {
@@ -127,7 +127,7 @@ class Sp804 : public AmbaDevice
     };
 
     /** Pointer to the GIC for causing an interrupt */
-    Gic *gic;
+    BaseGic *gic;
 
     /** Timers that do the actual work */
     Timer timer0;