ARM: Fix up the implmentation of the mrs instruction.
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1 changed files with 4 additions and 2 deletions
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@ -110,7 +110,9 @@ format DataOp {
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}
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1: decode MISC_OPCODE {
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0x0: decode OPCODE {
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0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }});
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0x8: PredOp::mrs_cpsr({{
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Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
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}});
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0x9: PredOp::msr_cpsr({{
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//assert(!RN<1:0>);
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if (OPCODE_18) {
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@ -120,7 +122,7 @@ format DataOp {
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CondCodes = mbits(Rm, 31,27);
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}
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}});
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0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}});
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0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
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0xb: WarnUnimpl::msr_spsr();
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}
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0x1: decode OPCODE {
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