misc: Fix issues flagged by gcc 6

A few warnings (and thus errors) pop up after being added to -Wall:

1. -Wmisleading-indentation

In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.

2. -Wshift-negative-value

gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.

That is all. Porting done.
This commit is contained in:
Andreas Hansson 2016-04-13 12:13:44 -04:00
parent 4b802a09c5
commit 8127c4e7bf
2 changed files with 10 additions and 7 deletions

View file

@ -2939,29 +2939,32 @@ let {{
twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True) twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True)
vsriCode = ''' vsriCode = '''
if (imm >= sizeof(Element) * 8) if (imm >= sizeof(Element) * 8) {
destElem = destElem; destElem = destElem;
else } else {
destElem = (srcElem1 >> imm) | destElem = (srcElem1 >> imm) |
(destElem & ~mask(sizeof(Element) * 8 - imm)); (destElem & ~mask(sizeof(Element) * 8 - imm));
}
''' '''
twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True) twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True)
twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True) twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True)
vshlCode = ''' vshlCode = '''
if (imm >= sizeof(Element) * 8) if (imm >= sizeof(Element) * 8) {
destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1; destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1;
else } else {
destElem = srcElem1 << imm; destElem = srcElem1 << imm;
}
''' '''
twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode) twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode)
twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode) twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode)
vsliCode = ''' vsliCode = '''
if (imm >= sizeof(Element) * 8) if (imm >= sizeof(Element) * 8) {
destElem = destElem; destElem = destElem;
else } else {
destElem = (srcElem1 << imm) | (destElem & mask(imm)); destElem = (srcElem1 << imm) | (destElem & mask(imm));
}
''' '''
twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True) twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True)
twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True) twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True)

View file

@ -45,7 +45,7 @@ DMASequencer::init()
{ {
RubyPort::init(); RubyPort::init();
m_is_busy = false; m_is_busy = false;
m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); m_data_block_mask = mask(RubySystem::getBlockSizeBits());
for (const auto &s_port : slave_ports) for (const auto &s_port : slave_ports)
s_port->sendRangeChange(); s_port->sendRangeChange();