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gcc: Add extra parens to quell warnings.

Browse source 
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
This commit is contained in:
Nathan Binkert 2008-09-27 21:03:49 -07:00
parent cf7ddd8e8a
commit 80d9be86e6
21 changed files with 57 additions and 57 deletions
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4
src/arch/alpha/ev5.hh
View file

@ -80,7 +80,7 @@ Phys2K0Seg(Addr addr)
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)
{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@ -90,7 +90,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg)
{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }

4
src/arch/alpha/pagetable.hh
View file

@ -57,9 +57,9 @@ struct VAddr
Addr level3() const
{ return PteAddr(addr >> PageShift); }
Addr level2() const
{ return PteAddr(addr >> NPtePageShift + PageShift); }
{ return PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
{ return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
{ return PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
struct PageTableEntry

4
src/arch/alpha/utility.hh
View file

@ -53,14 +53,14 @@ inline bool
isCallerSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
}
inline bool
isCalleeSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
return (reg >= 9 && reg <= 15);
return reg >= 9 && reg <= 15;
}
inline bool

4
src/arch/mips/dsp.cc
View file

@ -923,10 +923,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
for (int i = 0; i<2; i++) {
r_values[i] =
dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
r_values[i + 2] =
dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
}

26
src/arch/mips/isa/decoder.isa
View file

@ -416,16 +416,16 @@ decode OPCODE_HI default Unknown::unknown() {
Ctrl_Base_DepTag);
break;
case 25:
data = 0 | fcsr_val & 0xFE000000 >> 24
| fcsr_val & 0x00800000 >> 23;
data = (fcsr_val & 0xFE000000 >> 24)
| (fcsr_val & 0x00800000 >> 23);
break;
case 26:
data = 0 | fcsr_val & 0x0003F07C;
data = fcsr_val & 0x0003F07C;
break;
case 28:
data = 0 | fcsr_val & 0x00000F80
| fcsr_val & 0x01000000 >> 21
| fcsr_val & 0x00000003;
data = (fcsr_val & 0x00000F80)
| (fcsr_val & 0x01000000 >> 21)
| (fcsr_val & 0x00000003);
break;
case 31:
data = fcsr_val;
@ -1963,7 +1963,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode OP_LO {
format IntOp {
0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }});
}
}
0x2: decode OP_LO {
@ -2050,11 +2050,11 @@ decode OPCODE_HI default Unknown::unknown() {
format LoadUnalignedMemory {
0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
Rt.uw = mem_word << mem_shift |
Rt.uw & mask(mem_shift);
(Rt.uw & mask(mem_shift));
}});
0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
mem_word >> mem_shift;
Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
(mem_word >> mem_shift);
}});
}
}
@ -2069,12 +2069,12 @@ decode OPCODE_HI default Unknown::unknown() {
format StoreUnalignedMemory {
0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
uint32_t mem_shift = 32 - reg_shift;
mem_word = mem_word & (mask(reg_shift) << mem_shift) |
Rt.uw >> reg_shift;
mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
(Rt.uw >> reg_shift);
}});
0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
mem_word = Rt.uw << reg_shift |
mem_word & (mask(reg_shift));
(mem_word & (mask(reg_shift)));
}});
}
format CP0Control {

4
src/arch/mips/pagetable.hh
View file

@ -59,9 +59,9 @@ namespace MipsISA {
Addr level3() const
{ return MipsISA::PteAddr(addr >> PageShift); }
Addr level2() const
{ return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
{ return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
{ return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
{ return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry

2
src/arch/mips/utility.cc
View file

@ -145,7 +145,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
{
int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
cc_val << cc_idx |
bits(fcsr, cc_idx - 1, 0);

2
src/arch/sparc/faults.cc
View file

@ -546,7 +546,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, 2);
} else if (level == Hyperprivileged ||
level == Privileged && trapType() >= 384) {
(level == Privileged && trapType() >= 384)) {
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, trapType());
} else {

7
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -314,10 +314,11 @@ let {{
# are split into ones that are available in priv and hpriv, and
# those that are only available in hpriv
AlternateASIPrivFaultCheck = '''
if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
!AsiIsUnPriv((ASI)EXT_ASI)) ||
(!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
fault = new PrivilegedAction;
else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
fault = new PrivilegedAction;
'''

8
src/arch/sparc/tlb.cc
View file

@ -562,7 +562,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
asi = (ASI)req->getAsi();
bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
bool unaligned = (vaddr & size-1);
bool unaligned = vaddr & (size - 1);
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
vaddr, size, asi);
@ -801,8 +801,8 @@ handleIntRegAccess:
return new PrivilegedAction;
}
if (asi == ASI_SWVR_UDB_INTR_W && !write ||
asi == ASI_SWVR_UDB_INTR_R && write) {
if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
(asi == ASI_SWVR_UDB_INTR_R && write)) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
@ -822,7 +822,7 @@ handleQueueRegAccess:
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new PrivilegedAction;
}
if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}

2
src/arch/x86/emulenv.cc
View file

@ -91,7 +91,7 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
if (base != INTREG_RBP && base != INTREG_RSP ||
if ((base != INTREG_RBP && base != INTREG_RSP) ||
0/*Has an immediate offset*/) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction

4
src/arch/x86/insts/microop.cc
View file

@ -98,7 +98,7 @@ namespace X86ISA
case ConditionTests::SxOF:
return ccflags.sf ^ ccflags.of;
case ConditionTests::SxOvZF:
return ccflags.sf ^ ccflags.of | ccflags.zf;
return (ccflags.sf ^ ccflags.of) | ccflags.zf;
case ConditionTests::False:
return false;
case ConditionTests::NotECF:
@ -131,7 +131,7 @@ namespace X86ISA
case ConditionTests::NotSxOF:
return !(ccflags.sf ^ ccflags.of);
case ConditionTests::NotSxOvZF:
return !(ccflags.sf ^ ccflags.of | ccflags.zf);
return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
}
panic("Unknown condition: %d\n", condition);
return true;

8
src/arch/x86/predecoder.cc
View file

@ -319,17 +319,17 @@ namespace X86ISA
if (emi.mode.submode != SixtyFourBitMode &&
!csAttr.defaultSize) {
//figure out 16 bit displacement size
if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2)
if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
displacementSize = 2;
else if(modRM.mod == 1)
else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
} else {
//figure out 32/64 bit displacement size
if(modRM.mod == 0 && modRM.rm == 5 || modRM.mod == 2)
if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
displacementSize = 4;
else if(modRM.mod == 1)
else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;

2
src/arch/x86/regfile.cc
View file

@ -214,7 +214,7 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
//If we need to fold over the index to match byte semantics, do that.
//Otherwise, just strip off any extra bits and pass it through.
if (reg & (1 << 6))
return (reg & ~(1 << 6) - 0x4);
return (reg & (~(1 << 6) - 0x4));
else
return (reg & ~(1 << 6));
}

4
src/base/circlebuf.cc
View file

@ -208,7 +208,7 @@ CircleBuf::write(const char *b, int len)
_rollover = true;
}
if (old_start > old_stop && old_start < _stop ||
old_start < old_stop && _stop < old_stop)
if ((old_start > old_stop && old_start < _stop) ||
(old_start < old_stop && _stop < old_stop))
_start = _stop + 1;
}

6
src/base/intmath.hh
View file

@ -197,9 +197,9 @@ roundDown(T val, int align)
inline bool
isHex(char c)
{
return c >= '0' && c <= '9' ||
c >= 'A' && c <= 'F' ||
c >= 'a' && c <= 'f';
return (c >= '0' && c <= '9') ||
(c >= 'A' && c <= 'F') ||
(c >= 'a' && c <= 'f');
}
inline bool

6
src/base/random_mt.cc
View file

@ -123,15 +123,15 @@ Random::genrand()
int kk;
for (kk = 0; kk < N - M; kk++) {
y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK;
y = (mt[kk] & UPPER_MASK) | (mt[kk+1] & LOWER_MASK);
mt[kk] = mt[kk + M] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
for (; kk < N - 1; kk++) {
y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK;
y = (mt[kk] & UPPER_MASK) | (mt[kk+1] & LOWER_MASK);
mt[kk] = mt[kk + (M - N)] ^ (y >> 1) ^ mag01[y & 0x1UL];
}
y = mt[N - 1] & UPPER_MASK | mt[0] & LOWER_MASK;
y = (mt[N - 1] & UPPER_MASK) | (mt[0] & LOWER_MASK);
mt[N - 1] = mt[M - 1] ^ (y >> 1) ^ mag01[y & 0x1UL];
mti = 0;

8
src/base/stats/text.cc
View file

@ -191,8 +191,8 @@ struct ScalarPrint
void
ScalarPrint::operator()(ostream &stream) const
{
if (flags & nozero && value == 0.0 ||
flags & nonan && isnan(value))
if ((flags & nozero && value == 0.0) ||
(flags & nonan && isnan(value)))
return;
stringstream pdfstr, cdfstr;
@ -474,8 +474,8 @@ DistPrint::operator()(ostream &stream) const
print.flags = flags | __substat;
for (int i = 0; i < size; ++i) {
if (flags & nozero && vec[i] == 0.0 ||
flags & nonan && isnan(vec[i]))
if ((flags & nozero && vec[i] == 0.0) ||
(flags & nonan && isnan(vec[i])))
continue;
_min = i * bucket_size + min;

2
src/cpu/o3/cpu.cc
View file

@ -604,7 +604,7 @@ FullO3CPU<Impl>::suspendContext(int tid)
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
bool deallocated = deallocateContext(tid, false, 1);
// If this was the last thread then unschedule the tick event.
if (activeThreads.size() == 1 && !deallocated ||
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
_status = Idle;

2
src/dev/alpha/tsunami_cchip.cc
View file

@ -109,7 +109,7 @@ TsunamiCChip::read(PacketPtr pkt)
panic("TSDEV_CC_MTR not implemeted\n");
break;
case TSDEV_CC_MISC:
pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) |
(pkt->req->getCpuNum() & 0x3));
break;
case TSDEV_CC_AAR0:

3
src/dev/terminal.cc
View file

@ -294,8 +294,7 @@ Terminal::out(char c)
if (DTRACE(Terminal)) {
static char last = '\0';
if (c != '\n' && c != '\r' ||
last != '\n' && last != '\r') {
if ((c != '\n' && c != '\r') || (last != '\n' && last != '\r')) {
if (c == '\n' || c == '\r') {
int size = linebuf.size();
char *buffer = new char[size + 1];