arm, kvm: remove KvmGic
KvmGic functionality has been subsumed within the new MuxingKvmGic model, which has Pl390 fallback when not using KVM for fast emulation. This simplifies configuration and will enable checkpointing between KVM emulation and full-system simulation. Change-Id: Ie61251720064c512843015c075e4ac419a4081e8 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Curtis Dunham
parent
092b06b745
commit
80c17d0a8d
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@ -38,20 +38,7 @@
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from m5.params import *
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from m5.proxy import *
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from Gic import BaseGic, Pl390
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from KvmVM import KvmVM
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from System import System
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class KvmGic(BaseGic):
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type = 'KvmGic'
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cxx_header = "arch/arm/kvm/gic.hh"
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dist_addr = Param.Addr(0x1f001000, "Address for distributor")
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cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
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it_lines = Param.UInt32(128, "Number of interrupt lines supported")
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system = Param.System(Parent.any,
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'System this interrupt controller belongs to')
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from Gic import Pl390
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class MuxingKvmGic(Pl390):
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type = 'MuxingKvmGic'
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@ -44,7 +44,6 @@
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#include "arch/arm/kvm/base_cpu.hh"
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#include "debug/Interrupt.hh"
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#include "params/KvmGic.hh"
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#include "params/MuxingKvmGic.hh"
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KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
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@ -106,88 +105,6 @@ KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
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}
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KvmGic::KvmGic(const KvmGicParams *p)
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: BaseGic(p),
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system(*p->system),
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kernelGic(*system.getKvmVM(),
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p->cpu_addr, p->dist_addr, p->it_lines),
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addrRanges{kernelGic.distRange, kernelGic.cpuRange}
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{
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}
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KvmGic::~KvmGic()
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{
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}
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void
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KvmGic::serialize(CheckpointOut &cp) const
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{
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panic("Checkpointing unsupported\n");
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}
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void
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KvmGic::unserialize(CheckpointIn &cp)
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{
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panic("Checkpointing unsupported\n");
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}
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Tick
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KvmGic::read(PacketPtr pkt)
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{
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panic("KvmGic: PIO from gem5 is currently unsupported\n");
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}
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Tick
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KvmGic::write(PacketPtr pkt)
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{
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panic("KvmGic: PIO from gem5 is currently unsupported\n");
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}
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void
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KvmGic::sendInt(uint32_t num)
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{
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DPRINTF(Interrupt, "Set SPI %d\n", num);
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kernelGic.setSPI(num);
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}
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void
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KvmGic::clearInt(uint32_t num)
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{
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DPRINTF(Interrupt, "Clear SPI %d\n", num);
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kernelGic.clearSPI(num);
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}
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void
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KvmGic::sendPPInt(uint32_t num, uint32_t cpu)
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{
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DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
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kernelGic.setPPI(cpu, num);
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}
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void
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KvmGic::clearPPInt(uint32_t num, uint32_t cpu)
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{
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DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
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kernelGic.clearPPI(cpu, num);
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}
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void
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KvmGic::verifyMemoryMode() const
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{
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if (!(system.isAtomicMode() && system.bypassCaches())) {
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fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the "
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"current memory mode does not support KVM.\n");
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}
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}
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KvmGic *
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KvmGicParams::create()
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{
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return new KvmGic(this);
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}
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MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
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: Pl390(p),
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system(*p->system),
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@ -44,7 +44,6 @@
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#include "arch/arm/system.hh"
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#include "cpu/kvm/device.hh"
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#include "cpu/kvm/vm.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/arm/gic_pl390.hh"
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#include "dev/platform.hh"
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@ -138,74 +137,6 @@ class KvmKernelGicV2
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KvmDevice kdev;
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};
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struct KvmGicParams;
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/**
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* In-kernel GIC model.
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*
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* When using a KVM-based CPU model, it is possible to offload GIC
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* emulation to the kernel. This reduces some overheads when the guest
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* accesses the GIC and makes it possible to use in-kernel
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* architected/generic timer emulation.
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*
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* This device uses interfaces with the kernel GicV2 model that is
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* documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
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* Linux kernel sources.
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*
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* This GIC model has the following known limitations:
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* <ul>
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* <li>Checkpointing is not supported.
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* <li>This model only works with kvm. Simulated CPUs are not
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* supported since this would require the kernel to inject
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* interrupt into the simulated CPU.
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* </ul>
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*
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* @warn This GIC model cannot be used with simulated CPUs!
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*/
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class KvmGic : public BaseGic
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{
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public: // SimObject / Serializable / Drainable
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KvmGic(const KvmGicParams *p);
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~KvmGic();
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void startup() override { verifyMemoryMode(); }
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void drainResume() override { verifyMemoryMode(); }
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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public: // PioDevice
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AddrRangeList getAddrRanges() const { return addrRanges; }
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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public: // BaseGic
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void sendInt(uint32_t num) override;
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void clearInt(uint32_t num) override;
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void sendPPInt(uint32_t num, uint32_t cpu) override;
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void clearPPInt(uint32_t num, uint32_t cpu) override;
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protected:
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/**
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* Do memory mode sanity checks
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*
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* This method only really exists to warn users that try to switch
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* to a simulate CPU. There is no fool proof method to detect
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* simulated CPUs, but checking that we're in atomic mode and
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* bypassing caches should be robust enough.
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*/
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void verifyMemoryMode() const;
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/** System this interrupt controller belongs to */
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System &system;
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/** Kernel GIC device */
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KvmKernelGicV2 kernelGic;
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/** Union of all memory */
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const AddrRangeList addrRanges;
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};
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struct MuxingKvmGicParams;
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