inorder: remove unused file
inst_buffer file isn't used , so remove it
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e65c15e931
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800e93f358
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/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <vector>
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#include <list>
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resources/inst_buffer.hh"
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#include "cpu/inorder/cpu.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu)
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: Resource(res_name, res_id, res_width, res_latency, _cpu)
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{ }
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ResReqPtr
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InstBuffer::getRequest(DynInstPtr inst, int stage_num, int res_idx,
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int slot_num)
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{
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// After this is working, change this to a reinterpret cast
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// for performance considerations
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InstBufferEntry* ib_entry = dynamic_cast<InstBufferEntry*>(inst->resSched.top());
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assert(ib_entry);
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return new InstBufferRequest(this, inst, stage_num, id, slot_num,
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ib_entry->cmd);
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}
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void
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InstBuffer::execute(int slot_idx)
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{
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// After this is working, change this to a reinterpret cast
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// for performance considerations
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InstBufferRequest* ib_req = dynamic_cast<InstBufferRequest*>(reqMap[slot_idx]);
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assert(ib_req);
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DynInstPtr inst = ib_req->inst;
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ThreadID tid = inst->readTid();
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int seq_num = inst->seqNum;
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ib_req->fault = NoFault;
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switch (ib_req->cmd)
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{
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case InsertInst:
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{
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DPRINTF(Resource, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
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tid, seq_num);
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insert(inst);
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ib_req->done();
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}
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break;
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case RemoveInst:
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{
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DPRINTF(Resource, "[tid:%i]: Removing [sn:%i] from buffer.\n",
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tid, seq_num);
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remove(inst);
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ib_req->done();
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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DPRINTF(Resource, "Buffer now contains %i insts.\n", instList.size());
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}
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void
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InstBuffer::insert(DynInstPtr inst)
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{
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instList.push_back(inst);
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}
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void
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InstBuffer::remove(DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = instList.begin();
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std::list<DynInstPtr>::iterator list_end = instList.end();
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while (list_it != list_end) {
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if((*list_it) == inst) {
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instList.erase(list_it);
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break;
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}
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list_it++;
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}
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}
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void
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InstBuffer::pop()
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{ instList.pop_front(); }
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ThePipeline::DynInstPtr
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InstBuffer::top()
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{ return instList.front(); }
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void
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InstBuffer::squash(InstSeqNum squash_seq_num, ThreadID tid)
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{
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list<DynInstPtr>::iterator list_it = instList.begin();
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list<DynInstPtr>::iterator list_end = instList.end();
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queue<list<DynInstPtr>::iterator> remove_list;
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// Collect All Instructions to be Removed in Remove List
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while (list_it != list_end) {
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if((*list_it)->seqNum > squash_seq_num) {
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DPRINTF(Resource, "[tid:%i]: Squashing [sn:%i] in resource.\n",
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tid, (*list_it)->seqNum);
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(*list_it)->setSquashed();
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remove_list.push(list_it);
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}
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list_it++;
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}
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// Removed Instructions from InstList & Clear Remove List
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while (!remove_list.empty()) {
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instList.erase(remove_list.front());
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remove_list.pop();
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}
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Resource::squash(squash_seq_num, tid);
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}
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@ -1,109 +0,0 @@
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/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_INST_BUFF_UNIT_HH__
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#define __CPU_INORDER_INST_BUFF_UNIT_HH__
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#include <vector>
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#include <list>
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#include <string>
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#include "cpu/inorder/resource.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/cpu.hh"
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class InstBuffer : public Resource {
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public:
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typedef InOrderDynInst::DynInstPtr DynInstPtr;
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public:
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enum Command {
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InsertInst,
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InsertAddr,
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RemoveInst,
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RemoveAddr
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};
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public:
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InstBuffer(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu);
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virtual ~InstBuffer() {}
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virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num);
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virtual void execute(int slot_num);
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virtual void insert(DynInstPtr inst);
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virtual void remove(DynInstPtr inst);
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virtual void pop();
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virtual DynInstPtr top();
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virtual void squash(InstSeqNum squash_seq_num, ThreadID tid);
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protected:
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/** List of instructions this resource is currently
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* processing.
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*/
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std::list<DynInstPtr> instList;
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/** @todo: Add Resource Stats Here */
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};
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struct InstBufferEntry : public ThePipeline::ScheduleEntry {
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InstBufferEntry(int stage_num, int res_num, InstBuffer::Command _cmd) :
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ScheduleEntry(stage_num, res_num), cmd(_cmd)
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{ }
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InstBuffer::Command cmd;
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};
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class InstBufferRequest : public ResourceRequest {
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public:
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typedef InOrderDynInst::DynInstPtr DynInstPtr;
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public:
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InstBufferRequest(InstBuffer *res, DynInstPtr inst, int stage_num, int res_idx, int slot_num,
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InstBuffer::Command _cmd)
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: ResourceRequest(res, inst, stage_num, res_idx, slot_num),
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cmd(_cmd)
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{ }
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InstBuffer::Command cmd;
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};
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#endif //__CPU_INORDER_INST_BUFF_UNIT_HH__
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