diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 276310dd2..015f93805 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -369,4 +369,22 @@ let {{
     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
     exec_output += PredOpExecute.subst(uxtahIop)
+
+    selCode = '''
+        uint32_t resTemp = 0;
+        for (unsigned i = 0; i < 4; i++) {
+            int low = i * 8;
+            int high = low + 7;
+            replaceBits(resTemp, high, low,
+                        bits(CondCodes, 16 + i) ?
+                            bits(Op1, high, low) : bits(Op2, high, low));
+        }
+        Dest = resTemp;
+    '''
+    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
+                           { "code": selCode,
+                             "predicate_test": predicateTest }, [])
+    header_output += RegRegRegOpDeclare.subst(selIop)
+    decoder_output += RegRegRegOpConstructor.subst(selIop)
+    exec_output += PredOpExecute.subst(selIop)
 }};