Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
This commit is contained in:
commit
7f3dfa7c09
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@ -117,7 +117,7 @@ output exec {{
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/** return data in cases where there the size of data is only
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known in the packet
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*/
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uint64_t getStoreData(Packet *packet) {
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uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
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switch (packet->getSize())
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{
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case 8:
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@ -542,7 +542,7 @@ def template StoreCompleteAcc {{
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if (fault == NoFault) {
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%(op_wb)s;
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if (traceData) { traceData->setData(getStoreData(pkt)); }
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if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
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}
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return fault;
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@ -107,7 +107,7 @@ class MipsDynInst : public BaseDynInst<Impl>
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscReg(int misc_reg)
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MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
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{
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return this->cpu->readMiscReg(misc_reg, this->threadNumber);
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}
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@ -122,12 +122,13 @@ class MipsDynInst : public BaseDynInst<Impl>
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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*/
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void setMiscReg(int misc_reg, const MiscReg &val)
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void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
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{
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return this->cpu->setMiscReg(misc_reg, val,
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this->threadNumber);
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}
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/** Calls a syscall. */
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void syscall(int64_t callnum);
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@ -206,6 +207,55 @@ class MipsDynInst : public BaseDynInst<Impl>
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BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
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}
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/** Reads a miscellaneous register. */
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TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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return this->cpu->readMiscRegNoEffect(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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this->threadNumber);
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}
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/** Reads a misc. register, including any side-effects the read
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* might have as defined by the architecture.
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*/
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TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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return this->cpu->readMiscReg(
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si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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this->threadNumber);
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}
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/** Sets a misc. register. */
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void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
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{
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this->instResult.integer = val;
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return this->cpu->setMiscRegNoEffect(
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si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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val, this->threadNumber);
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}
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/** Sets a misc. register, including any side-effects the write
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* might have as defined by the architecture.
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*/
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void setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val)
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{
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return this->cpu->setMiscReg(
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si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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val, this->threadNumber);
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}
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uint64_t readRegOtherThread(int misc_reg)
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{
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panic("MIPS MT not defined for O3 CPU.\n");
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return 0;
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}
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void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
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{
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panic("MIPS MT not defined for O3 CPU.\n");
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}
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public:
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/** Calculates EA part of a memory instruction. Currently unused,
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* though it may be useful in the future if we want to split
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