Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.

mem/mem_object.hh:
    Create constrtor so it compiles
mem/packet.hh:
    Fix typedefs so they compile, add in a few more headers for compilation
mem/page_table.cc:
    convert to new mem system so it compiles
mem/page_table.hh:
    fix it to the version that had asid support.  Make it compile in the new system
mem/physical.cc:
    Fix some compilation bugs
mem/physical.hh:
    Add a type that made compile fail
mem/port.hh:
    Fix a spelling error that messed up compilation
mem/request.hh:
    fix typedefs and forward declerations so it compiles

--HG--
extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
This commit is contained in:
Ron Dreslinski 2006-02-15 14:21:09 -05:00
parent 3298e937d3
commit 7f114ca419
8 changed files with 133 additions and 79 deletions

View file

@ -41,8 +41,13 @@
* The base MemoryObject class, allows for an accesor function to a * The base MemoryObject class, allows for an accesor function to a
* simobj that returns the Port. * simobj that returns the Port.
*/ */
class MemoryObject : public SimObject class MemObject : public SimObject
{ {
public:
MemObject(const std::string &name)
: SimObject(name)
{};
public: public:
/** Additional function to return the Port of a memory object. */ /** Additional function to return the Port of a memory object. */
virtual Port *getPort(const char *if_name) = 0; virtual Port *getPort(const char *if_name) = 0;

View file

@ -36,6 +36,12 @@
#define __MEM_PACKET_HH__ #define __MEM_PACKET_HH__
#include "mem/request.hh" #include "mem/request.hh"
#include "targetarch/isa_traits.hh"
#include "sim/root.hh"
struct Packet;
typedef Packet* PacketPtr;
typedef uint8_t* PacketDataPtr;
/** List of all commands associated with a packet. */ /** List of all commands associated with a packet. */
enum Command enum Command
@ -54,8 +60,6 @@ enum PacketResult
class SenderState{}; class SenderState{};
class Coherence{}; class Coherence{};
typedef PacketDataPtr *unit8_t;
/** /**
* A Packet is the structure to handle requests between two levels * A Packet is the structure to handle requests between two levels
* of the memory system. The Request is a global object that trancends * of the memory system. The Request is a global object that trancends
@ -118,6 +122,4 @@ struct Packet
short getDest() const { return dest; } short getDest() const { return dest; }
}; };
typedef PacketPtr *Packet;
#endif //__MEM_PACKET_HH #endif //__MEM_PACKET_HH

View file

@ -34,34 +34,40 @@
#include <map> #include <map>
#include <fstream> #include <fstream>
#include "base/bitfield.hh" using namespace std;
#include "base/intmath.hh" #include "base/intmath.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "mem/mem_cmd.hh" #include "mem/physical.hh"
#include "mem/mem_req.hh"
#include "mem/page_table.hh" #include "mem/page_table.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
#include "sim/system.hh"
using namespace std; PageTable::PageTable(const std::string &name)
: SimObject(name)
PageTable::PageTable(System *_system, Addr _pageSize)
: pageSize(_pageSize), offsetMask(mask(FloorLog2(_pageSize))),
system(_system)
{ {
assert(IsPowerOf2(pageSize));
} }
PageTable::~PageTable() PageTable::~PageTable()
{ {
//Iterate the page table freeing the memoruy
//Addr addr;
//std::map<Addr,Addr>::iterator iter;
//iter = pTable.begin();
//while(iter != pTable.end())
//{
//delete [] (uint8_t *)iter->second;
// iter ++;
// }
} }
Fault Fault
PageTable::page_check(Addr addr, int size) const PageTable::page_check(Addr addr, int size) const
{ {
if (size < sizeof(uint64_t)) { if (size < sizeof(uint64_t)) {
if (!IsPowerOf2(size)) { if (!isPowerOf2(size)) {
panic("Invalid request size!\n"); panic("Invalid request size!\n");
return Machine_Check_Fault; return Machine_Check_Fault;
} }
@ -83,49 +89,78 @@ PageTable::page_check(Addr addr, int size) const
} }
void
PageTable::allocate(Addr vaddr, int size)
{
// starting address must be page aligned
assert(pageOffset(vaddr) == 0);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
if (iter != pTable.end()) {
// already mapped
fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
}
pTable[vaddr] = system->new_page();
}
}
bool
PageTable::translate(Addr vaddr, Addr &paddr)
{
Addr page_addr = pageAlign(vaddr);
std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
if (iter == pTable.end()) {
return false;
}
paddr = iter->second + pageOffset(vaddr);
return true;
}
Fault Fault
PageTable::translate(MemReqPtr &req) PageTable::translate(CpuRequestPtr &req)
{ {
assert(pageAlign(req->vaddr + req->size - 1) == pageAlign(req->vaddr)); //Should I check here for accesses that are > VMPageSize?
if (!translate(req->vaddr, req->paddr)) { req->paddr = translate(req->vaddr, req->asid);
return Machine_Check_Fault;
}
return page_check(req->paddr, req->size); return page_check(req->paddr, req->size);
} }
Addr
PageTable::translate(Addr vaddr, unsigned asid)
{
Addr hash_addr;
std::map<Addr,Addr>::iterator iter;
//DPRINTF(PageTable,"PageTable: Virtual Address %#x Translating for ASID %i\n",
// vaddr,asid);
//Create the hash_addr
//Combine vaddr and asid
hash_addr = vaddr & (~(VMPageSize - 1)) | asid;
//DPRINTF(PageTable,"PageTable: Hash Address %#x\n",hash_addr);
//Look into the page table
iter=pTable.find(hash_addr);
//bool page_fault = true;
//Store the translated address if found, and return
if (iter != pTable.end()) //Found??
{
Addr return_addr = iter->second + (vaddr & (VMPageSize - 1));
return return_addr;
}
else//Alocate a new page, register translation
{
Addr return_addr;
//DPRINTF(PageTable,"PageTable: Page Not Found. Allocating new page\n");
Addr new_page = mem->new_page();
pTable[hash_addr] = new_page;
return_addr = new_page + (vaddr & (VMPageSize - 1));
return return_addr;
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PageTable)
SimObjectParam<PhysicalMemory *> physmem;
END_DECLARE_SIM_OBJECT_PARAMS(PageTable)
BEGIN_INIT_SIM_OBJECT_PARAMS(PageTable)
INIT_PARAM_DFLT(physmem, "Pointer to functional memory", NULL)
END_INIT_SIM_OBJECT_PARAMS(PageTable)
CREATE_SIM_OBJECT(PageTable)
{
PageTable *pTable = new PageTable(getInstanceName());
if (physmem)
pTable->setPhysMem(physmem);
return pTable;
}
REGISTER_SIM_OBJECT("PageTable", PageTable)

View file

@ -38,50 +38,51 @@
#include <map> #include <map>
#include "base/trace.hh" #include "base/trace.hh"
#include "mem/mem_req.hh" #include "mem/request.hh"
#include "mem/mem_cmd.hh" #include "mem/packet.hh"
#include "sim/sim_object.hh" #include "sim/sim_object.hh"
class System; class PhysicalMemory;
/** /**
* Page Table Decleration. * Page Table Decleration.
*/ */
class PageTable class PageTable : public SimObject
{ {
protected: protected:
std::map<Addr,Addr> pTable; std::map<Addr,Addr> pTable;
const Addr pageSize; PhysicalMemory *mem;
const Addr offsetMask;
System *system;
public: public:
PageTable(System *_system, Addr _pageSize = VMPageSize); /**
* Construct this interface.
* @param name The name of this interface.
* @param hier Pointer to the hierarchy wide parameters.
* @param _mem the connected memory.
*/
PageTable(const std::string &name);
~PageTable(); ~PageTable();
Addr pageAlign(Addr a) { return (a & ~offsetMask); } void setPhysMem(PhysicalMemory *_mem) { mem = _mem; }
Addr pageOffset(Addr a) { return (a & offsetMask); }
Fault page_check(Addr addr, int size) const; Fault page_check(Addr addr, int size) const;
void allocate(Addr vaddr, int size);
/** /**
* Translate function * Translate function
* @param vaddr The virtual address. * @param vaddr The virtual address.
* @param asid The address space id.
* @return Physical address from translation. * @return Physical address from translation.
*/ */
bool translate(Addr vaddr, Addr &paddr); Addr translate(Addr vaddr, unsigned asid);
/** /**
* Perform a translation on the memory request, fills in paddr field of mem_req. * Perform a translation on the memory request, fills in paddr field of mem_req.
* @param req The memory request. * @param req The memory request.
*/ */
Fault translate(MemReqPtr &req); Fault translate(CpuRequestPtr &req);
}; };

View file

@ -43,11 +43,12 @@
#if FULL_SYSTEM #if FULL_SYSTEM
#include "mem/functional/memory_control.hh" #include "mem/functional/memory_control.hh"
#endif #endif
#include "mem/functional/physical.hh" #include "mem/physical.hh"
#include "sim/host.hh" #include "sim/host.hh"
#include "sim/builder.hh" #include "sim/builder.hh"
#include "targetarch/isa_traits.hh" #include "targetarch/isa_traits.hh"
using namespace std; using namespace std;
#if FULL_SYSTEM #if FULL_SYSTEM
@ -89,7 +90,7 @@ PhysicalMemory::PhysicalMemory(const string &n, Range<Addr> range,
#endif #endif
PhysicalMemory::PhysicalMemory(const string &n) PhysicalMemory::PhysicalMemory(const string &n)
: FunctionalMemory(n), base_addr(0), pmem_addr(NULL) : Memory(n), base_addr(0), pmem_addr(NULL)
{ {
// Hardcoded to 128 MB for now. // Hardcoded to 128 MB for now.
pmem_size = 1 << 27; pmem_size = 1 << 27;

View file

@ -78,6 +78,7 @@ class PhysicalMemory : public Memory
virtual void unserialize(Checkpoint *cp, const std::string &section); virtual void unserialize(Checkpoint *cp, const std::string &section);
}; };
uint64_t
PhysicalMemory::phys_read_qword(Addr addr) const PhysicalMemory::phys_read_qword(Addr addr) const
{ {
if (addr + sizeof(uint64_t) > pmem_size) if (addr + sizeof(uint64_t) > pmem_size)

View file

@ -120,7 +120,7 @@ class Port
an object wants to own some ranges and snoop on others, it will an object wants to own some ranges and snoop on others, it will
need to use two different ports. need to use two different ports.
*/ */
virtual void recvAddressRangeQuery(std::list<Range<Addr> > &range_list, virtual void recvAddressRangesQuery(std::list<Range<Addr> > &range_list,
bool &owner) = 0; bool &owner) = 0;
public: public:

View file

@ -34,9 +34,18 @@
#ifndef __MEM_REQUEST_HH__ #ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__ #define __MEM_REQUEST_HH__
#include "targetarch/isa_traits.hh"
class Request;
class CpuRequest;
typedef Request* RequestPtr;
typedef CpuRequest* CpuRequestPtr;
class Request class Request
{ {
//@todo Make Accesor functions, make these private.
public:
/** The physical address of the request. */ /** The physical address of the request. */
Addr paddr; Addr paddr;
@ -53,10 +62,10 @@ class Request
Addr copyDest; Addr copyDest;
}; };
typedef RequestPtr *Request;
class CpuRequest : public Request class CpuRequest : public Request
{ {
//@todo Make Accesor functions, make these private.
public:
/** The virtual address of the request. */ /** The virtual address of the request. */
Addr vaddr; Addr vaddr;