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MI data corruption bug fix

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This commit is contained in:
Polina Dudnik 2009-09-11 10:59:35 -05:00
parent 353a69eae7
commit 7ef3e3b2c2
1 changed files with 32 additions and 17 deletions
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49
src/mem/protocol/MI_example-dir.sm
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@ -21,7 +21,8 @@ machine(Directory, "Directory protocol")
M_DRD, desc="Blocked on an invalidation for a DMA read"; M_DRD, desc="Blocked on an invalidation for a DMA read";
M_DWR, desc="Blocked on an invalidation for a DMA write"; M_DWR, desc="Blocked on an invalidation for a DMA write";
M_DWRI, desc="Intermediate state M_DWR-->I"; M_DWRI, desc="Intermediate state M_DWR-->I";
M_DRDI, desc="Intermediate state M_DRD-->I";
IM, desc="Intermediate state I-->M"; IM, desc="Intermediate state I-->M";
MI, desc="Intermediate state M-->I"; MI, desc="Intermediate state M-->I";
@ -306,11 +307,11 @@ machine(Directory, "Directory protocol")
action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
peek(dmaRequestQueue_in, DMARequestMsg) { peek(dmaRequestQueue_in, DMARequestMsg) {
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
out_msg.Address := address; out_msg.Address := address;
out_msg.Type := CoherenceRequestType:INV; out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := machineID; out_msg.Requestor := machineID;
out_msg.Destination := directory[in_msg.PhysicalAddress].Owner; out_msg.Destination := directory[in_msg.PhysicalAddress].Owner;
out_msg.MessageSize := MessageSizeType:Writeback_Control; out_msg.MessageSize := MessageSizeType:Writeback_Control;
} }
} }
} }
@ -323,16 +324,15 @@ machine(Directory, "Directory protocol")
dmaRequestQueue_in.dequeue(); dmaRequestQueue_in.dequeue();
} }
action(l_writeDataToMemory, "l", desc="Write PUTX data to memory") { action(l_writeDataToMemory, "pl", desc="Write PUTX data to memory") {
peek(requestQueue_in, RequestMsg) { peek(requestQueue_in, RequestMsg) {
// assert(in_msg.Dirty); // assert(in_msg.Dirty);
// assert(in_msg.MessageSize == MessageSizeType:Writeback_Data); // assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
directory[in_msg.Address].DataBlk := in_msg.DataBlk; directory[in_msg.Address].DataBlk := in_msg.DataBlk;
DEBUG_EXPR(in_msg.Address); //directory[in_msg.Address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
DEBUG_EXPR(in_msg.DataBlk);
} }
} }
action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") { action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len); directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
} }
@ -416,7 +416,8 @@ machine(Directory, "Directory protocol")
out_msg.Address := address; out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.OriginalRequestorMachId := in_msg.Requestor; out_msg.OriginalRequestorMachId := in_msg.Requestor;
//out_msg.DataBlk := in_msg.DataBlk; // get incoming data
// out_msg.DataBlk := in_msg.DataBlk;
out_msg.DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len); out_msg.DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
out_msg.MessageSize := in_msg.MessageSize; out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch; //out_msg.Prefetch := in_msg.Prefetch;
@ -448,23 +449,26 @@ machine(Directory, "Directory protocol")
} }
action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") { action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
directory[address].DataBlk := TBEs[address].DataBlk; //directory[address].DataBlk := TBEs[address].DataBlk;
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
} }
// TRANSITIONS // TRANSITIONS
transition({M_DRD, M_DWR, M_DWRI}, GETX) { transition({M_DRD, M_DWR, M_DWRI, M_DRDI}, GETX) {
z_recycleRequestQueue; z_recycleRequestQueue;
} }
transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) { transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) {
z_recycleRequestQueue; z_recycleRequestQueue;
} }
transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) { transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) {
y_recycleDMARequestQueue; y_recycleDMARequestQueue;
} }
transition(I, GETX, IM) { transition(I, GETX, IM) {
//d_sendData; //d_sendData;
qf_queueMemoryFetchRequest; qf_queueMemoryFetchRequest;
@ -507,18 +511,27 @@ machine(Directory, "Directory protocol")
} }
transition(M, DMA_READ, M_DRD) { transition(M, DMA_READ, M_DRD) {
v_allocateTBE;
inv_sendCacheInvalidate; inv_sendCacheInvalidate;
p_popIncomingDMARequestQueue; p_popIncomingDMARequestQueue;
} }
transition(M_DRD, PUTX, I) { transition(M_DRD, PUTX, M_DRDI) {
l_writeDataToMemory;
drp_sendDMAData; drp_sendDMAData;
c_clearOwner; c_clearOwner;
a_sendWriteBackAck; l_queueMemoryWBRequest;
d_deallocateDirectory;
i_popIncomingRequestQueue; i_popIncomingRequestQueue;
} }
transition(M_DRDI, Memory_Ack, I) {
l_sendWriteBackAck;
w_deallocateTBE;
d_deallocateDirectory;
l_popMemQueue;
}
transition(M, DMA_WRITE, M_DWR) { transition(M, DMA_WRITE, M_DWR) {
v_allocateTBE; v_allocateTBE;
inv_sendCacheInvalidate; inv_sendCacheInvalidate;
@ -526,6 +539,7 @@ machine(Directory, "Directory protocol")
} }
transition(M_DWR, PUTX, M_DWRI) { transition(M_DWR, PUTX, M_DWRI) {
l_writeDataToMemory;
qw_queueMemoryWBRequest_partialTBE; qw_queueMemoryWBRequest_partialTBE;
c_clearOwner; c_clearOwner;
i_popIncomingRequestQueue; i_popIncomingRequestQueue;
@ -547,6 +561,7 @@ machine(Directory, "Directory protocol")
} }
transition(M, PUTX, MI) { transition(M, PUTX, MI) {
l_writeDataToMemory;
c_clearOwner; c_clearOwner;
v_allocateTBEFromRequestNet; v_allocateTBEFromRequestNet;
l_queueMemoryWBRequest; l_queueMemoryWBRequest;