ARM: Remove the special naming from the new version of data processing instructions.
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4f08b52af2
commit
7eb3ea2798
2 changed files with 49 additions and 49 deletions
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@ -40,18 +40,18 @@ def format ArmDataProcReg() {{
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case %(opcode)#x:
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if (immShift) {
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if (setCc) {
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return new %(className)sDRegCc(machInst, %(dest)s, %(op1)s,
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return new %(className)sRegCc(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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} else {
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return new %(className)sDReg(machInst, %(dest)s, %(op1)s,
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return new %(className)sReg(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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}
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} else {
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if (setCc) {
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return new %(className)sDRegRegCc(machInst, %(dest)s,
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return new %(className)sRegRegCc(machInst, %(dest)s,
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%(op1)s, rm, rs, type);
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} else {
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return new %(className)sDRegReg(machInst, %(dest)s,
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return new %(className)sRegReg(machInst, %(dest)s,
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%(op1)s, rm, rs, type);
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}
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}
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@ -105,10 +105,10 @@ def format ArmDataProcImm() {{
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instDecode = '''
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case %(opcode)#x:
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if (setCc) {
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return new %(className)sDImmCc(machInst, %(dest)s, %(op1)s,
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return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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} else {
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return new %(className)sDImm(machInst, %(dest)s, %(op1)s,
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return new %(className)sImm(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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}
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break;
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@ -168,30 +168,30 @@ def format Thumb16ShiftAddSubMoveCmp() {{
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
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switch (bits(machInst, 13, 11)) {
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case 0x0: // lsl
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
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return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
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case 0x1: // lsr
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
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return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
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case 0x2: // asr
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
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return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
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case 0x3:
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switch (bits(machInst, 10, 9)) {
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case 0x0:
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return new AddDReg(machInst, rd, rn, rm, 0, LSL);
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return new AddReg(machInst, rd, rn, rm, 0, LSL);
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case 0x1:
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return new SubDReg(machInst, rd, rn, rm, 0, LSL);
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return new SubReg(machInst, rd, rn, rm, 0, LSL);
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case 0x2:
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return new AddDImm(machInst, rd, rn, imm3, true);
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return new AddImm(machInst, rd, rn, imm3, true);
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case 0x3:
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return new SubDImm(machInst, rd, rn, imm3, true);
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return new SubImm(machInst, rd, rn, imm3, true);
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}
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case 0x4:
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return new MovDImm(machInst, rd8, INTREG_ZERO, imm8, true);
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return new MovImm(machInst, rd8, INTREG_ZERO, imm8, true);
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case 0x5:
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return new CmpDImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
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return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
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case 0x6:
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return new AddDImm(machInst, rd8, rd8, imm8, true);
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return new AddImm(machInst, rd8, rd8, imm8, true);
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case 0x7:
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return new SubDImm(machInst, rd8, rd8, imm8, true);
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return new SubImm(machInst, rd8, rd8, imm8, true);
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}
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}
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'''
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@ -204,38 +204,38 @@ def format Thumb16DataProcessing() {{
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
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switch (bits(machInst, 9, 6)) {
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case 0x0:
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return new AndDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x1:
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return new EorDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x2: //lsl
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
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return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
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case 0x3: //lsr
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
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return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
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case 0x4: //asr
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
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return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
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case 0x5:
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return new AdcDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x6:
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return new SbcDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x7: // ror
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
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return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
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case 0x8:
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return new TstDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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return new TstReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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case 0x9:
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return new RsbDImm(machInst, rdn, rm, 0, true);
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return new RsbImm(machInst, rdn, rm, 0, true);
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case 0xa:
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return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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case 0xb:
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return new CmnDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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return new CmnReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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case 0xc:
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return new OrrDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0xd:
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//XXX Implement me!
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return new WarnUnimplemented("mul", machInst);
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case 0xe:
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return new BicDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0xf:
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return new MvnDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
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return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
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}
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}
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'''
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@ -250,11 +250,11 @@ def format Thumb16SpecDataAndBx() {{
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
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switch (bits(machInst, 9, 8)) {
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case 0x0:
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return new AddDReg(machInst, rdn, rdn, rm, 0, LSL);
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return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x1:
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return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
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case 0x2:
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return new MovDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
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return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
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case 0x3:
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if (bits(machInst, 7) == 0)
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return new WarnUnimplemented("bx", machInst);
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@ -271,7 +271,7 @@ def format Thumb16Adr() {{
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{
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const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
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const uint32_t imm8 = bits(machInst, 7, 0) << 2;
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return new AddDImm(machInst, rd, INTREG_PC, imm8, true);
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return new AddImm(machInst, rd, INTREG_PC, imm8, true);
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}
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'''
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}};
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@ -281,7 +281,7 @@ def format Thumb16AddSp() {{
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{
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const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
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const uint32_t imm8 = bits(machInst, 7, 0) << 2;
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return new AddDImm(machInst, rd, INTREG_SP, imm8, true);
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return new AddImm(machInst, rd, INTREG_SP, imm8, true);
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}
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'''
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}};
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@ -292,10 +292,10 @@ def format Thumb16Misc() {{
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switch (bits(machInst, 11, 8)) {
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case 0x0:
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if (bits(machInst, 7)) {
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return new SubDImm(machInst, INTREG_SP, INTREG_SP,
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return new SubImm(machInst, INTREG_SP, INTREG_SP,
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bits(machInst, 6, 0) << 2, true);
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} else {
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return new AddDImm(machInst, INTREG_SP, INTREG_SP,
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return new AddImm(machInst, INTREG_SP, INTREG_SP,
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bits(machInst, 6, 0) << 2, true);
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}
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case 0x1:
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@ -376,10 +376,10 @@ def format Thumb32DataProcModImm() {{
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def decInst(mnem, dest="rd", op1="rn"):
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return '''
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if (s) {
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return new %(mnem)sDImmCc(machInst, %(dest)s,
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return new %(mnem)sImmCc(machInst, %(dest)s,
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%(op1)s, imm, true);
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} else {
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return new %(mnem)sDImm(machInst, %(dest)s,
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return new %(mnem)sImm(machInst, %(dest)s,
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%(op1)s, imm, true);
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}
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''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
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@ -468,10 +468,10 @@ def format Thumb32DataProcShiftReg() {{
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def decInst(mnem, dest="rd", op1="rn"):
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return '''
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if (s) {
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return new %(mnem)sDRegCc(machInst, %(dest)s,
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return new %(mnem)sRegCc(machInst, %(dest)s,
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%(op1)s, rm, amt, type);
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} else {
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return new %(mnem)sDReg(machInst, %(dest)s,
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return new %(mnem)sReg(machInst, %(dest)s,
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%(op1)s, rm, amt, type);
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}
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''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
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@ -126,26 +126,26 @@ let {{
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immCode = secondOpRe.sub(immOp2, code)
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regCode = secondOpRe.sub(regOp2, code)
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regRegCode = secondOpRe.sub(regRegOp2, code)
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immIop = InstObjParams(mnem, mnem.capitalize() + "DImm", "DataImmOp",
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immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
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{"code" : immCode,
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"predicate_test": predicateTest})
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regIop = InstObjParams(mnem, mnem.capitalize() + "DReg", "DataRegOp",
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regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
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{"code" : regCode,
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"predicate_test": predicateTest})
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regRegIop = InstObjParams(mnem, mnem.capitalize() + "DRegReg",
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regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
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"DataRegRegOp",
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{"code" : regRegCode,
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"predicate_test": predicateTest})
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "DImmCc",
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
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"DataImmOp",
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{"code" : immCode + immCcCode,
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"predicate_test": predicateTest})
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "DRegCc",
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": predicateTest})
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regRegIopCc = InstObjParams(mnem + "s",
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mnem.capitalize() + "DRegRegCc",
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mnem.capitalize() + "RegRegCc",
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"DataRegRegOp",
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{"code" : regRegCode + regRegCcCode,
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"predicate_test": predicateTest})
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