ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue.
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -155,6 +156,10 @@ structure (CacheMemory, external = "yes") {
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void recordRequestType(CacheRequestType);
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void recordRequestType(CacheRequestType);
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bool checkResourceAvailable(CacheResourceType, Address);
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bool checkResourceAvailable(CacheResourceType, Address);
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int getCacheSize();
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int getNumBlocks();
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Address getAddressAtIdx(int);
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Scalar demand_misses;
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Scalar demand_misses;
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Scalar demand_hits;
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Scalar demand_hits;
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}
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}
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -134,6 +135,29 @@ CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
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return -1; // Not found
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return -1; // Not found
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}
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}
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// Given an unique cache block identifier (idx): return the valid address
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// stored by the cache block. If the block is invalid/notpresent, the
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// function returns the 0 address
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Address
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CacheMemory::getAddressAtIdx(int idx) const
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{
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Address tmp(0);
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int set = idx / m_cache_assoc;
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assert(set < m_cache_num_sets);
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int way = idx - set * m_cache_assoc;
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assert (way < m_cache_assoc);
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AbstractCacheEntry* entry = m_cache[set][way];
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if (entry == NULL ||
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entry->m_Permission == AccessPermission_Invalid ||
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entry->m_Permission == AccessPermission_NotPresent) {
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return tmp;
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}
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return entry->m_Address;
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}
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bool
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bool
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CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
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CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
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DataBlock*& data_ptr)
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DataBlock*& data_ptr)
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -131,6 +132,10 @@ class CacheMemory : public SimObject
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Stats::Scalar numTagArrayStalls;
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Stats::Scalar numTagArrayStalls;
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Stats::Scalar numDataArrayStalls;
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Stats::Scalar numDataArrayStalls;
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int getCacheSize() const { return m_cache_size; }
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int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
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Address getAddressAtIdx(int idx) const;
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private:
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private:
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// convert a Address to its location in the cache
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// convert a Address to its location in the cache
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int64 addressToCacheSet(const Address& address) const;
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int64 addressToCacheSet(const Address& address) const;
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