sanchayanmaity
/
gem5
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm: remove SCTLR.FI 

Removed from ARMARM.

Change-Id: Ie8f28e4fa6e1b46dfd9c8c4b379e5b42fe25421d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Curtis Dunham 2016-12-19 11:03:27 -06:00
parent 19d90956eb
commit 7ddb55a5f2
1 changed files with 8 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
src/arch/arm/isa.cc
View File

@ -776,24 +776,14 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
return readMiscRegNoEffect(MISCREG_IFAR_S);
case MISCREG_HVBAR: // bottom bits reserved
return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
case MISCREG_SCTLR: // Some bits hardwired
// The FI field (bit 21) is common between S/NS versions of the register
return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
(readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
case MISCREG_SCTLR:
return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
case MISCREG_SCTLR_EL1:
// The FI field (bit 21) is common between S/NS versions of the register
return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
(readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
return (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800;
case MISCREG_SCTLR_EL3:
// The FI field (bit 21) is common between S/NS versions of the register
return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) |
(readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
case MISCREG_HSCTLR: // FI comes from SCTLR
{
uint32_t mask = 1 << 27;
return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
(readMiscRegNoEffect(MISCREG_SCTLR) & mask);
}
return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
case MISCREG_HSCTLR:
return readMiscRegNoEffect(MISCREG_HSCTLR);
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
@ -1111,18 +1101,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_SCTLR:
{
DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
MiscRegIndex sctlr_idx;
scr = readMiscRegNoEffect(MISCREG_SCR);
if (haveSecurity && !scr.ns) {
sctlr_idx = MISCREG_SCTLR_S;
} else {
sctlr_idx = MISCREG_SCTLR_NS;
// The FI field (bit 21) is common between S/NS versions
// of the register, we store this in the secure copy of
// the reg
miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21);
miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
}
MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;