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config: Fix 'learning gem5' configs after SMT push

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This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.
This commit is contained in:
Andreas Hansson 2015-10-01 04:07:15 -04:00
parent 02881a7bf3
commit 7dd171ba96
2 changed files with 6 additions and 6 deletions
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6
configs/learning_gem5/part1/simple.py
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@ -70,9 +70,9 @@ system.cpu.createInterruptController()
# For x86 only, make sure the interrupts are connected to the memory # For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached # Note: these are directly connected to the memory bus and are not cached
if m5.defines.buildEnv['TARGET_ISA'] == "x86": if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.cpu.interrupts.pio = system.membus.master system.cpu.interrupts[0].pio = system.membus.master
system.cpu.interrupts.int_master = system.membus.slave system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts.int_slave = system.membus.master system.cpu.interrupts[0].int_slave = system.membus.master
# Create a DDR3 memory controller and connect it to the membus # Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DDR3_1600_x64() system.mem_ctrl = DDR3_1600_x64()

6
configs/learning_gem5/part1/two_level.py
View file

@ -120,9 +120,9 @@ system.cpu.createInterruptController()
# For x86 only, make sure the interrupts are connected to the memory # For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached # Note: these are directly connected to the memory bus and are not cached
if m5.defines.buildEnv['TARGET_ISA'] == "x86": if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.cpu.interrupts.pio = system.membus.master system.cpu.interrupts[0].pio = system.membus.master
system.cpu.interrupts.int_master = system.membus.slave system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts.int_slave = system.membus.master system.cpu.interrupts[0].int_slave = system.membus.master
# Connect the system up to the membus # Connect the system up to the membus
system.system_port = system.membus.slave system.system_port = system.membus.slave